Category Archives: XCell Articles

Descriptions and links to all articles written for Xilinx Xcell Journal

A Double-Barreled Way to Get the Most from Your Zynq SoC

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One of the many benefits
of the Xilinx® Zynq®-7000
All Programmable SoC is
that it is has two ARM®
Cortex™-A9 processors
onboard. However, many
bare-metal applications and simpler operating
systems use only one of the two
ARM cores in the Zynq SoC’s processing
system (PS), a design choice that can potentially
limit system performance.
Depending upon the application in development,
there could, however, be a need
to have both processors running bare-metal
applications, or to run different operating
systems on each of the processors. For
instance, one side could be performing
critical calculations and hence running a
bare-metal/RTOS application while the second
processor is providing HMI and communications
using Linux.

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Design Reliability: MTBF Is Just the Beginning Issue 88

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When most engineers think about design reliability, their minds turn to a single, central metric: mean time between failures. MTBF is, in fact, an important parameter in assessing how dependable your design will be. But another factor, probability of success, is just as crucial, and you would do well to take note of other considerations as well to ensure an accurate reliability analysis and, ultimately, a reliable solution.

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Calculating Mathematically Complex Functions Issue 87

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Thanks to their flexibility and performance,
FPGAs have found
their way into a number of industrial,
science, military and other
applications that require the calculation
of complex mathematical problems
or transfer functions. It is not uncommon to
see tight accuracy and calculation latency
times in the more critical applications.
When using an FPGA to implement mathematical
functions, engineers normally
choose fixed-point mathematics (see Xcell
Journal issue 80, “The Basics of FPGA
Mathematics,” http://issuu.com/xcelljournal/
docs/xcell80/44?e=2232228/2002872).
Also, there are many algorithms, such as
CORDIC, that you can use to calculate transcendental
functions (see Xcell Journal issue
79, “How to Use the CORDIC Algorithm
in Your FPGA,” http://www.xilinx.com/
publications/archives/xcel l/Xcell79.pdf).
However, when confronting functions that
are very mathematically complex, there are
more efficient ways of dealing with them than
by implementing the exact demanding function
within the FPGA. To understand these
alternative approaches—especially one of
them, polynomial approximation—let us first
define the problem.

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How to use Interrupts on the Zynq SoC Issue 87

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In embedded processing, an interrupt is
a signal that temporarily halts the processor’s
current activities. The processor
saves its current state and executes
an interrupt service routine to address
the reason for the interrupt. An interrupt can
come from one of the three following places:
• Hardware – An electronic signal connected
directly to the processor
• Software – A software instruction loaded by
the processor
• Exception – An exception generated by the
processor when an error or exceptional
event occurs
Regardless of the source, interrupts can also
be classified as either maskable or non-maskable.
You can safely ignore a maskable interrupt
by setting the appropriate bit in an interrupt
mask register. But you cannot ignore a
non-maskable interrupt, because these are the
types typically used for timers and watchdogs.
Interrupts can be either edge triggered or
level triggered. The Xilinx® Zynq®-7000 All Programmable
SoC supports configuration of the
interrupt either way, as we will see later.

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Ins and Outs of Creating the Optimal Testbench Issue 86

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Verification of an FPGA or RTL module can be a time-consuming process as the engineer strives to ensure the design will function correctly against its requirement specification and against corner cases that could make the module go awry. Engineers traditionally achieve this verification using a testbench, a file that you will devise to test your design. However, testbenches can be simple or complicated affairs. Let us have a look at how we can get the most from our testbench without overcomplicating it.

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How to Add a RTOS to your Zynq SoC Design Issue 86

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In the quest to gain the maximum benefit from the processing system within a Xilinx® Zynq®-7000 All Programmable SoC, an operating system will get you further than a simple bare-metal solution. Anyone developing a Zynq SoC design has a large number of operating systems to choose from, and depending upon the end application you may opt for a real-time version. An RTOS is your best choice if you are using the Zynq SoC in industrial, military, aerospace or other challenging environments where response times and reliable performance are required to prevent loss of life or injury, or to achieve strict performance goals

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A Pain-Free Way to Bring Up Your Hardware Design Issue 85

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One of the most exciting
moments in an engineering
project is when the
hardware arrives in the lab
for the first time, ready for commissioning
before integration testing. This
stage in the development process typically
can mean long hours and a certain
amount of stress for all the engineers
on the project. But tools and
techniques are available to help ease
the way and move the project along.
Let’s take a look at how we can minimize
any issues that may arise in getting
a design to the next level, and how
to get through the commissioning
phase in a timely manner.

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Implementing Analog Mixed Signal on the Zynq SoC

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The Xilinx® Zynq® All Programmable
SoC comes with an XADC block
that contains two 12-bit analog-todigital
converters. These ADCs are capable
of sampling at up to 1 Megasample per second
(MSPS), providing an ideal effective
input-signal bandwidth of 500 kHz (250 kHz
on the auxiliary inputs). The XADC can multiplex
among 17 inputs along with a number
of internal voltages and temperatures. If
your design is pin-limited in terms of available
analog-capable inputs for external signals,
you can configure the XADC to drive an
external analog multiplexer and sequence
through all the inputs in the desired order.

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How to Boost Zynq Performance by Creating Your Own Peripheral issue 84

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One of the real advantages of the Xilinx® Zynq™-
7000 All Programmable SoC is the ability to
increase the performance of the processing system
(PS) side of the device by creating a peripheral within
the programmable logic (PL) side. At first you might
think this would be a complicated job. However, it is surprisingly
simple to create your own peripheral.
Adding a peripheral within the PL can be of great
help when you’re trying to speed up the performance
of your processing system or when you’re using the
PS to control the behavior of the design within the
programmable logic side. For example, the PS might
use a number of memory-mapped registers to control
operations or options for the design within the programmable
logic.

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