How to Configure Your Zynq SoC Bare-Metal Solution Issue 83

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Because of its unique mix of ARM processing
clout and FPGA logic in a single device, the
Zynq™-7000 All Programmable SoC requires a
twofold configuration process, one that takes into
account both the processor system and the programmable
logic. Engineers will find that the configuration
sequence differs slightly from that of traditional
Xilinx® FPGAs. Nevertheless, the methodology is
familiar and it’s not at all difficult to generate a boot
image and program the configuration memory.
Where standard FPGA configuration practices normally
require only the FPGA bit file, you will need to
add a second type of configuration file to get the maximum
benefit from your Zynq SoC: the SW Executable
and Linakble Format (ELF) file. The FPGA bit file
defines the behavior of the programmable logic section
of your design, while ELF file is the software program
that the processing system will execute.
So let’s have a look at how to implement a baremetal
(no operating system) software application on
your Zynq SoC.

Link here 

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