Tag Archives: vhdl

FPGA Forum 2015 Key Note

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The last 20 years have seen the explosion of FPGA technology used in many different end applications, including those within harsh environments. It therefore follows that system developers wish these devices to operate correctly and safely regardless of environment. When engineers design for a space flight mission, there are a number of environmental factors that may impact mission performance: radiation; temperature; and the dynamic environment. How much weighting each of these environmental factors has depends upon the end space application which are typically grouped into one of three categories Launcher, Science / Exploration or Telecommunication.  Regardless of the end application the engineer must consider FPGA technology, Mitigation strategies at both the FPGA and System level along with lessons learned from previous missions. However, these techniques and mitigation strategies are not just limited to space applications but can also be applied to terrestrial applications

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Calculating Mathematically Complex Functions Issue 87

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Thanks to their flexibility and performance,
FPGAs have found
their way into a number of industrial,
science, military and other
applications that require the calculation
of complex mathematical problems
or transfer functions. It is not uncommon to
see tight accuracy and calculation latency
times in the more critical applications.
When using an FPGA to implement mathematical
functions, engineers normally
choose fixed-point mathematics (see Xcell
Journal issue 80, “The Basics of FPGA
Mathematics,” http://issuu.com/xcelljournal/
docs/xcell80/44?e=2232228/2002872).
Also, there are many algorithms, such as
CORDIC, that you can use to calculate transcendental
functions (see Xcell Journal issue
79, “How to Use the CORDIC Algorithm
in Your FPGA,” http://www.xilinx.com/
publications/archives/xcel l/Xcell79.pdf).
However, when confronting functions that
are very mathematically complex, there are
more efficient ways of dealing with them than
by implementing the exact demanding function
within the FPGA. To understand these
alternative approaches—especially one of
them, polynomial approximation—let us first
define the problem.

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How to use Interrupts on the Zynq SoC Issue 87

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In embedded processing, an interrupt is
a signal that temporarily halts the processor’s
current activities. The processor
saves its current state and executes
an interrupt service routine to address
the reason for the interrupt. An interrupt can
come from one of the three following places:
• Hardware – An electronic signal connected
directly to the processor
• Software – A software instruction loaded by
the processor
• Exception – An exception generated by the
processor when an error or exceptional
event occurs
Regardless of the source, interrupts can also
be classified as either maskable or non-maskable.
You can safely ignore a maskable interrupt
by setting the appropriate bit in an interrupt
mask register. But you cannot ignore a
non-maskable interrupt, because these are the
types typically used for timers and watchdogs.
Interrupts can be either edge triggered or
level triggered. The Xilinx® Zynq®-7000 All Programmable
SoC supports configuration of the
interrupt either way, as we will see later.

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Ins and Outs of Creating the Optimal Testbench Issue 86

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Verification of an FPGA or RTL module can be a time-consuming process as the engineer strives to ensure the design will function correctly against its requirement specification and against corner cases that could make the module go awry. Engineers traditionally achieve this verification using a testbench, a file that you will devise to test your design. However, testbenches can be simple or complicated affairs. Let us have a look at how we can get the most from our testbench without overcomplicating it.

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How to Boost Zynq Performance by Creating Your Own Peripheral issue 84

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One of the real advantages of the Xilinx® Zynq™-
7000 All Programmable SoC is the ability to
increase the performance of the processing system
(PS) side of the device by creating a peripheral within
the programmable logic (PL) side. At first you might
think this would be a complicated job. However, it is surprisingly
simple to create your own peripheral.
Adding a peripheral within the PL can be of great
help when you’re trying to speed up the performance
of your processing system or when you’re using the
PS to control the behavior of the design within the
programmable logic side. For example, the PS might
use a number of memory-mapped registers to control
operations or options for the design within the programmable
logic.

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How to Configure Your Zynq SoC Bare-Metal Solution Issue 83

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Because of its unique mix of ARM processing
clout and FPGA logic in a single device, the
Zynq™-7000 All Programmable SoC requires a
twofold configuration process, one that takes into
account both the processor system and the programmable
logic. Engineers will find that the configuration
sequence differs slightly from that of traditional
Xilinx® FPGAs. Nevertheless, the methodology is
familiar and it’s not at all difficult to generate a boot
image and program the configuration memory.
Where standard FPGA configuration practices normally
require only the FPGA bit file, you will need to
add a second type of configuration file to get the maximum
benefit from your Zynq SoC: the SW Executable
and Linakble Format (ELF) file. The FPGA bit file
defines the behavior of the programmable logic section
of your design, while ELF file is the software program
that the processing system will execute.
So let’s have a look at how to implement a baremetal
(no operating system) software application on
your Zynq SoC.

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How to Implement State Machines in Your FPGA Issue 81

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FPGAs are often called upon to perform
sequence- and control-based actions such as
implementing a simple communication protocol.
For a designer, the best way to address
these actions and sequences is by using a state
machine. State machines are logical constructs that transition
among a finite number of states. A state machine will be in
only one state at a particular point in time. It will, however,
move between states depending upon a number of triggers.

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The Basics of FPGA Mathematics Issue 80

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One of the many benefits of an FPGA-based solution
is the ability to implement a mathematical
algorithm in the best possible manner for the
problem at hand. For example, if response time
is critical, then we can pipeline the stages of mathematics.
But if accuracy of the result is more important, we can use
more bits to ensure we achieve the desired precision. Of
course, many modern FPGAs also provide the benefit of
embedded multipliers and DSP slices, which can be used to
obtain the optimal implementation in the target device.
Let’s take a look at the rules and techniques that you can
use to develop mathematical functions within an FPGA or
other programmable device.

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The Engineers Guide to using ADCs and DACs issue 80

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Once it’s performed the task it
was designed to do, an FPGAbased
system next has to interface
with the real world, and as every
engineer knows, the real world tends
to function around analog as opposed
to digital signals. That means conversion
is going to be required to and from
the digital domain from the analog
realm. Just as you face a plethora of
choices in selecting the correct FPGA
for the job at hand, so too will you find
an abundance of riches when choosing
the correct ADC or DAC for a system.

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