Tag Archives: Zynq

How to use Interrupts on the Zynq SoC Issue 87

Facebooktwittergoogle_plusredditpinterestlinkedinmail

xilinx87

In embedded processing, an interrupt is
a signal that temporarily halts the processor’s
current activities. The processor
saves its current state and executes
an interrupt service routine to address
the reason for the interrupt. An interrupt can
come from one of the three following places:
• Hardware – An electronic signal connected
directly to the processor
• Software – A software instruction loaded by
the processor
• Exception – An exception generated by the
processor when an error or exceptional
event occurs
Regardless of the source, interrupts can also
be classified as either maskable or non-maskable.
You can safely ignore a maskable interrupt
by setting the appropriate bit in an interrupt
mask register. But you cannot ignore a
non-maskable interrupt, because these are the
types typically used for timers and watchdogs.
Interrupts can be either edge triggered or
level triggered. The Xilinx® Zynq®-7000 All Programmable
SoC supports configuration of the
interrupt either way, as we will see later.

Link here

Facebooktwittergoogle_plusredditpinterestlinkedinmail

How to Add a RTOS to your Zynq SoC Design Issue 86

Facebooktwittergoogle_plusredditpinterestlinkedinmail

xilinx86-2

In the quest to gain the maximum benefit from the processing system within a Xilinx® Zynq®-7000 All Programmable SoC, an operating system will get you further than a simple bare-metal solution. Anyone developing a Zynq SoC design has a large number of operating systems to choose from, and depending upon the end application you may opt for a real-time version. An RTOS is your best choice if you are using the Zynq SoC in industrial, military, aerospace or other challenging environments where response times and reliable performance are required to prevent loss of life or injury, or to achieve strict performance goals

Link here

Facebooktwittergoogle_plusredditpinterestlinkedinmail

Implementing Analog Mixed Signal on the Zynq SoC

Facebooktwittergoogle_plusredditpinterestlinkedinmail

xilinx85

The Xilinx® Zynq® All Programmable
SoC comes with an XADC block
that contains two 12-bit analog-todigital
converters. These ADCs are capable
of sampling at up to 1 Megasample per second
(MSPS), providing an ideal effective
input-signal bandwidth of 500 kHz (250 kHz
on the auxiliary inputs). The XADC can multiplex
among 17 inputs along with a number
of internal voltages and temperatures. If
your design is pin-limited in terms of available
analog-capable inputs for external signals,
you can configure the XADC to drive an
external analog multiplexer and sequence
through all the inputs in the desired order.

Link here

Facebooktwittergoogle_plusredditpinterestlinkedinmail

How to Boost Zynq Performance by Creating Your Own Peripheral issue 84

Facebooktwittergoogle_plusredditpinterestlinkedinmail

xilinx84

 

One of the real advantages of the Xilinx® Zynq™-
7000 All Programmable SoC is the ability to
increase the performance of the processing system
(PS) side of the device by creating a peripheral within
the programmable logic (PL) side. At first you might
think this would be a complicated job. However, it is surprisingly
simple to create your own peripheral.
Adding a peripheral within the PL can be of great
help when you’re trying to speed up the performance
of your processing system or when you’re using the
PS to control the behavior of the design within the
programmable logic side. For example, the PS might
use a number of memory-mapped registers to control
operations or options for the design within the programmable
logic.

Link here

Facebooktwittergoogle_plusredditpinterestlinkedinmail

How to Configure Your Zynq SoC Bare-Metal Solution Issue 83

Facebooktwittergoogle_plusredditpinterestlinkedinmail

xilinx83_2

 

Because of its unique mix of ARM processing
clout and FPGA logic in a single device, the
Zynq™-7000 All Programmable SoC requires a
twofold configuration process, one that takes into
account both the processor system and the programmable
logic. Engineers will find that the configuration
sequence differs slightly from that of traditional
Xilinx® FPGAs. Nevertheless, the methodology is
familiar and it’s not at all difficult to generate a boot
image and program the configuration memory.
Where standard FPGA configuration practices normally
require only the FPGA bit file, you will need to
add a second type of configuration file to get the maximum
benefit from your Zynq SoC: the SW Executable
and Linakble Format (ELF) file. The FPGA bit file
defines the behavior of the programmable logic section
of your design, while ELF file is the software program
that the processing system will execute.
So let’s have a look at how to implement a baremetal
(no operating system) software application on
your Zynq SoC.

Link here 

Facebooktwittergoogle_plusredditpinterestlinkedinmail