Category Archives: XCell Articles

Descriptions and links to all articles written for Xilinx Xcell Journal

High Performance FPGA’s Take Flight in Micro Satellites Issue 75

Facebooktwittergoogle_plusredditpinterestlinkedinmail

xilinx75The UKube1 mission is the pilot mission for the U.K. Space
Agency’s planned CubeSat program. CubeSats are a class of
nanosatellites that are scalable from the basic 1U satellite
(10 x 10 x 10 cm) up to 3U (30 x 10 x 10 cm) and beyond, and which
are flown in low-earth orbit. The typical development cost of a
CubeSat payload is less than $100,000, and development time is
short. This combination makes CubeSats an ideal platform for verifying
new and exciting technologies in orbit without the associated
overhead or risks that would be present in flying these payloads on
a larger mission. Of course, this class of satellites can present its
own series of design challenges for the engineers involved.
The EADS Astrium payload for the UKube1 mission comprises
two experiments, both of which are FPGA based. The first experiment
is the validation of a patent held by Astrium on random-number
generation. True random-number generation is an essential component
of secure communications systems. The second experiment
is the flight of a large, high-performance Xilinx® Virtex®-4 FPGA
with the aim of achieving additional in-flight experience with this
technology while gaining an understanding of the device’s radiation
performance and capabilities in the low-earth orbit (LEO). Figure 1
shows the architecture of the payload.

Link here 

Facebooktwittergoogle_plusredditpinterestlinkedinmail

Using FPGA’s in Mission Critical Systems Issue 73

Facebooktwittergoogle_plusredditpinterestlinkedinmail

xilinx73

Dramatic surges in FPGA technology,
device size and capabilities have over the
last few years increased the number of
potential applications that FPGAs can
implement. Increasingly, these applications
are in areas that demand high reliability,
such as aerospace, automotive or
medical. Such applications must function
within a harsh operating environment,
which can also affect the system
performance. This demand for high reliability
coupled with use in rugged environments
often means you as the
engineer must take additional care in the
design and implementation of the state
machines (as well as all accompanying
logic) inside your FPGA to ensure they
can function within the requirements.
One of the major causes of errors within
state machines is single-event upsets
caused by either a high-energy neutron or
an alpha particle striking sensitive sections
of the device silicon. SEUs can cause a bit
to flip its state (0 -> 1 or 1 -> 0), resulting
in an error in device functionality that
could potentially lead to the loss of the system
or even endanger life if incorrectly
handled. Because these SEUs do not result
in any permanent damage to the device
itself, they are called soft errors.

link here

 

Facebooktwittergoogle_plusredditpinterestlinkedinmail