Tag Archives: Electronics

Edge Detection on Signals

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I was recently looking at some code for a friend who is learning VHDL (no, I am not going to name names as to who it was). Along the way, I came across an interesting mistake that they had made, and I thought this would make an excellent addition to our discussions here on All Programmable Planet.

The essence of the problem was that the coder was attempting to detect rising and falling edges on signals in a synthesisable module. Not unsurprisingly for someone new to VHDL working within a clocked process, they attempted to use the “rising_edge” and “falling_edge” functions to detect edges on the signals of interest. A snapshot of the code I was sent is demonstrated below. (I know there are additional issues with this code, but for the moment we will focus only upon the rising and falling edge usage.)

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Those who know VHDL will not be surprised to hear that when this code was synthesized, it didn’t not get very far before failing with the following message:

“Logic for signal is controlled by a clock but does not appear to be a valid sequential description.”

To a beginner this might be a little confusing. Why can’t you use the “rising_edge” and “falling_edge” functions to detect these edges? Actually, things can quickly become even more confusing, because it’s possible to create code that will simulate quite happily, but that will fail to synthesize as expected.

Now, if the sort of code shown above was being employed for something like a testbench (i.e., if you never intended to synthesizis this code), then — with a little tweaking (in the case of the example above) — it would simulate perfectly fine and everyone would be happy.

In fact, this is all tied up with the levels of abstraction that are possible with VHDL. If you create something at too high a level of abstraction, it is possible that your code might simulate and appear to function as desired, thereby giving rise to false confidence that your solution is valid and good progress is being made on the project, only to run into issues downstream. One reason for this is that, depending on your simulation tool settings (see the example shown below), you may fail to receive a warning on how synthesizable/unsynthesizable your code will be.

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In the case of our example code, the problem arises when we try and implement this code within an FPGA, because then we are working within the stricter confines of supported synthesizable instructions and templates.

Sadly, the example code presented earlier does fall outside the template recognized by most synthesis tools as a clocked process. This is due to the multiple “rising_edge” and “falling_edge” function calls, which make it impossible for the synthesis tool to determine which calls should clock the register elements and which calls are being used only to detect signal edges and hence are not clocking registers.

To ensure synthesis, your process must contain only one “rising_edge” or “falling_edge” function call as shown in the code below, which implements a simple D-Type register. (Some FPGAs do have flip-flops that support double data rate; i.e., data changing on both the rising and falling edge of the clock, but we will address these in a future column so as to keep things simple here.)

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So, how do we detect edges on signals within a design without using the “rising_edge” or “falling_edge” functions? Actually, this is very simple and can be achieved using two registers connected in series, such that one register contains the same signal as the other register, but delayed by one clock cycle. The engineer can then use the values contained within these registers to determine if the signal is indeed rising or falling.

So what does this actually look like in code and when implemented? Well, take a look at the code below along with the corresponding schematic diagram:

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Of course, the state of the “det_reg” could also be used in other synchronous processes and compared against a predefined constant to detect if the signal edge was rising or falling. This has the advantage that by simply changing the value of the constant, the type of edge being detected — and hence the action taken — can be changed without the need to modify the code itself.

 

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The Art of Decoupling

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Like the perfect temperature at which beer should be served, the design and location of a decoupling capacitor network will return different answers depending upon who is being asked. The funny thing is that although the answers may be very different, each respondent will be sure that he or she is the only one who is correct.

Before I discuss my preferred beer-serving temperature and I explain how I design and locate my decoupling capacitors, I think it is important we all understand why we have decoupling capacitor networks in the first place. These networks are intended to perform two functions as follows:

  1. To provide a low impedance path to ground for AC signals and noise signals that are superimposed on the DC supply voltage.
  2. To act as a local energy store close to the device being decoupled such that high frequency demands for current due to logic gates switching, for example, can be supplied without the voltage rail being affected. (Remember that a power supply has a much slower response time to transient demands than the operational speed of the devices it powers. Indeed, at higher frequencies, on-chip decoupling is required, but that’s a story for another day.)

Both of these requirements will have bearing on the design of the decoupling capacitor network. We must also understand the parasitic elements and construction of a real-world capacitor, which — along with its capacitive element — will also have resistive and inductive elements as illustrated below:

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Real structure of a capacitor (for decoupling purposes, RP is normally discounted).

Equivalent Series Resistance (ESR) is defined by the resistance of the leads or pads and losses in the dielectric; this is typically in the range of 0.01 to 0.1Ω for a ceramic capacitor.

Equivalent Series Inductance (ESL) is defined by internal connections or leads and pads. This is very important in the case of decoupling because it will dominate over the capacitance above certain frequencies.

From the model above, it is clear that the capacitor C and the ESL will form a series resonance creating a near short (it is not a dead short due to the ESR). You can calculate the Self Resonant Frequency (SRF) of a capacitor using the following equation:

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What this means is that if you have a specific AC frequency you wish to remove, then you should ideally select a capacitor that has a SRF at the relevant frequency. Another consideration is to ensure a low impedance profile over a wide frequency band, which will require a range of capacitor values connected in parallel. For example, the network illustrated below employs two different value capacitors; observe the fact that there are more lower-value capacitors than higher-value capacitors

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An example decoupling capacitor network.

When you are calculating this, do not forget the contribution of PCB inter-plane capacitance, which will dominate at high frequency. Inter-plane capacitance is achieved by careful design of the PCB stack to ensure that the power and ground planes are closely coupled within the stack, thereby creating capacitance.

It’s important to remember that the combined decoupling impedance is a function of all the different types and quantities of decoupling capacitors. The example below shows a combined decoupling capacitance (dark blue) formed by using 100nF capacitors (pink), 10nF capacitors (yellow), and 11µF capacitors (cyan/turquoise). In this case the combined decoupling impedance is required to be below 0.1Ω across a wide frequency range

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Decoupling impedance, which is required to be below 0.1Ω across a wide frequency range.

Your target impedance will be defined by the parameters of the voltage supply being decoupled, the maximum transient current, and the allowable ripple on the rail as described by the following equation:

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Having defined the target impedance, you can then use the capacitors available to you and their supplied information — capacitance, ESL, ESR, tolerance, and drift — to design a network that meets your impedance profile.

Your selection of decoupling capacitor will generally involve a ceramic device — commonly a multi-layer component — although polymer capacitors may be used for some applications. When it comes to selecting the most appropriate device, obviously you will start by looking for a low ESR and an acceptable SRF. You will also need to understand how the capacitor will operate across the desired temperature range and — more importantly — how the capacitance will change with temperature. For example, an X5R capacitor will work between -55 and +85°C with a change in capacitance of +/- 15% across the temperature range, while a Y7V capacitor will operate between -+30 and +125°C while exhibiting a variation of +22 to -82% of capacitance value — selecting the correct type is crucial.

Please remember to follow any recommendations made by the chip manufacturers also, because some devices have on-chip decoupling, which reduces the board-level decoupling requirements. The reasons for this will become clear in my next column in this miniseries.

Based on the discussions above, your decoupling network should now acknowledge the parasitic elements and component tolerances of the various capacitors you’ve selected. Sad to relate, however, this does not guarantee the final performance of the network. This is because we have not yet taken into account any parasitic parameters associated with the component mounting; nor have we considered the effects of component placement.

Whenever I talk to people about decoupling, they all say that the capacitor should be placed as close to the device as possible. However, very few people can actually tell me why this is and at what point “close enough” becomes “too far away.” As engineers, we need to understand what drives the placement of these components. Using this knowledge, we can define a series of rules regarding placement and layout such that the layout engineer is not simply just told to “put these as close as possible.” The lack of clear guidance can negatively impact the complexity of the design, the complexity of the manufacturing, and the cost of the circuit board.

A key aspect of decoupling is controlling the inductance associated with both the tracking and the mounting of the capacitor. Although the capacitor stores the charge, it is the inductance that determines the speed at which this charge can be delivered from the capacitor. Therefore, reducing the inductance loop is the most important aspect to consider when placing a capacitor.

This starts with the very design of the SMT (surface mount technology) capacitor mounting pads within your PCB library. Ideally the mounting via should be located as close as possible to the pad (though not within the pad unless you are using micro-via technology). If space permits, it is better to use multiple vias per pad as this reduces the overall inductance. You definitely do not want long thin tracks from the solder land to the via. Also, do not be tempted to share vias between capacitors.

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The inductance loop is defined as being the loop created between the mounting via and the connections to the voltage planes. For this reason, when you define the stack of your board and assign layers to power and ground, you need to assign higher priority power planes (those with higher current demands from the device being decoupled) to be higher in the stack because this reduces the vertical distance the current needs to travel before reaching the plane.

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When implemented correctly, the mounting inductance will be similar in value to the equivalent series inductance. This will have an impact on the resonant frequency (RF) of the capacitor, and hence should be included in the resonant frequency calculation. As the inductance increases, the resonant frequency — it is not the self-resonant frequency (SRF) as the mounting inductance is included — will be reduced:

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Once calculated, the RF for the mounted component tells us the frequency at which the capacitor is most effective. Thus, we can use this to determine how close the capacitor needs to be located to the device it is decoupling so as to be most effective.

As the device being decoupled demands more current, it will cause a disturbance in the local power plane, and the decoupling capacitor will attempt to counteract this. There is a finite time between the device demanding current and the capacitor sensing and acting upon this demand. The time delay is calculated as follows:

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You can determine the signal propagation speed in your circuit board by means of the following equation (where εr is the dialectic constant of the PCB material):

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It obviously takes the same time delay for the current supplied from the capacitor to reach the device; hence, there is a “round trip delay.” We can therefore use the propagation speed “Vp” to determine the effective wavelength of the capacitor at its mounted resonant frequency. This wavelength can then be used to determine how close to the device being decoupled the capacitor needs to be placed using the following rules:

  • When the capacitor is located more than a quarter of a wavelength away, the capacitor has no effect on the device being decoupled.
  • The energy transfer will increase the closer the capacitor is located to the device being decoupled.
  • An ideal target is to place capacitors within 1/40th of a wavelength. This means that smaller value capacitors have to be placed closer than do larger ones.

You can calculate the wavelength of the capacitor using the following equation:

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As was noted above, it’s good practice to locate the decoupling capacitors within 1/40th of the wavelength, which means you will have zones of decoupling as shown below:

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Priority should be given to termination resistors and discrete filtering capacitors for things like high-speed serial link power supplies over decoupling capacitors close to the device.

So now we understand the reasons why we decouple and how we go about doing this on the final design, including the rules outlining the placement of our decoupling capacitors. It is possible to verify the final layout using tools like HyperLynx Power Integrity from Mentor Graphics, which will not only look at DC drops across planes (this is just as important as decoupling) but also the AC performance

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