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Articles on Hardware Engineering

More things to consider for your prototype


Three things to consider for your prototyping

One of the most exciting stages of an engineering project is when the hardware arrives in the lab for the first time ready for commissioning before integration testing. This typically can mean long hours for all the engineers on the project so how can we try and reduce this time and minimize the issues which may arise.

  1. Think how you will test it from day one – All engineers know the cost of implementing fixes increases as the development progresses. It is more expensive to fix a pin out error once the design has been fixed and manufactured than during an early design review for example. This is the same for testing, thinking of how you will test it from day one and what test equipment you might need.
  2. Think about what to include in the design – During the design of the hardware several design features and functions may need to be included to allow testing of the board with greater ease. The most simple and often implemented test provision is placing test points on all voltage rails Being able to monitor the outputs of clocks and resets is also important, for this reason it is good practice to place test points on the reset line and correctly terminate an unused clock buffer and add test points allowing the clock to be probed with ease. Many modern high performance devices also have on die temperature diodes which can be used during your testing to determine the junction temperature of the die is acceptable, provided you can access these points.
  3. Simple RTL – If you have a complicated design at both the hardware and FPGA level it can be best to develop a more simplified cut down version of the RTL to aid in the testing of the board and the interface between the FPGA and the peripheral. This is especially the case if you are designing high speed interfaces. This cut down RTL could be used in conjunction with chip scope to capture data and block rams which have been pre loaded with data patterns to act as stimulus. This can especially be the case when using ADCs and DACs connected to a FPGA the reprogrammable nature of the FPGA should be utilized to the maximum to develop designs which will allow parametric testing of the ADC and DAC for instance Noise Power Ratio, Spurious Free Dynamic Range and effective number of bit calculations. You should also aim to capitalize on the resources provided by the FPGA  especially system monitor and XADC which can be very useful for monitoring the voltage rails on die and hence helping verify the power integrity analysis

What if it does not go to plan? The first thing to do is not panic, for many issues you will probably not be the first person to face this issue(s) though it may feel like it. Revisit the design schematics, layout and read the data sheets and any errata’s again also have a look on some of the very helpful websites like All Programmable Planet or the Xilinx Forums there are plenty of helpful ones out there.


Things to consider for your prototype


One the most exciting, fun and terrifying stages of engineering is when the first prototypes or engineering models arrive in the lab and are ready for testing. You will have been planning for this day for a long time (hopefully) as the cost of identifying and correcting errors later on in the production run only increases.

Planning for this day will have started right back at the concept of the design as you considered how you would test the functionality being designed into the hardware, FPGA and processors etc. Ensuring you have provided sufficient test points and protected them appropriately (you would hate to short out a rail as you tried to measure the voltage). One thing you also need to consider is accessibility of these test points and debug headers to ensure you can actually access them. Another aspect to consider is how you can test the board on its own will you need any special to type test equipment to enable you to test it, when will it be available.

You will also need to compile a test plan to detail everything you intend to test and the expected results otherwise how else can you be expected to know if performs as required or not.

Once you get the hardware in the lab the testing is generally split into two sections the section is checking the hardware integrity i.e. can it be powered on safely and is it suitable for further testing. During this stage you will check the board has been manufactured and populated correctly, that the voltage rails are safe to turn on and then will come the moment of truth when you have to apply power to the board for the first time. This is always a nerve wracking moment…

Once you have applied power you will be looking at the current drawn against your projections, are the clocks at the correct frequency, does the protection circuitry (over voltage / under voltage) resets and sequencing function as desired. This is the basic engineering tests that will be your first priority however; you will soon progress to wanting to test the more complex interfaces and then the performance.

Some of these may be able to be tested via JTAG / Boundary scan however it is only really testing at speed that you can relax a little (you can never truly relax even after all the qualification testing) It is therefore a great idea to have developed some simple test code for your FPGA or microprocessor to prevent you having to debug both the FPGA/Microprocessor design and the board design. I am sure we have all spent many hours looking into is the issue with the board, FPGA, processor or even worse the ASIC.

Once you have completed the integrity checks you can then proceed to testing the functionality and working out what changes you need to make to the next iteration if any.

Of course at some point I am sure you will encounter problems the most important thing to remember at that point is to not panic and attempt to determine the root cause of the issue even if there is nothing you can do about it on the prototype.


Hardware Considerations – Power Architectures Part One


One of the more interesting aspects to start looking at is the power architecture of a design, and how we go about powering FPGA’s (and other devices) on the board. Normally the system will have an intermediate voltage which comes from an AC/DC convertor or other DC supply which powers the system. The first stage of the design is to correctly specify this interface in terms of voltage and current required by the design. Determining this intermediate voltage is the easier task of the two, as the current required will have to take into account the downstream convertor efficiencies.

The first stage in defining power architecture is the determination of all the voltage rails and currents drawn by each of these rails. For example when considering a FPGA based imaging system as shown below you may have a number of voltage rails


For this example all of the power supplies have a requirement to be within +/-5%.


As can be seen from the table above the highest voltage required is 3.465V which is the 3.3V at its maximum acceptable tolerance. Knowing this value allows us to determine the voltage supplied by the AC/DC or other DC supply within the system, the sensible thing to do here is to select a convertor which has an output compatible with the 3.3V required and save a conversion stage (increasing the overall efficiency).

The next stage is to determine the power required by each of the rails. The requires that you use power estimation tools such as Xilinx XPE and read the datasheets for other devices to ensure you can determine the power required, I tend to collate all of this in a spread sheet as this comes in useful later on once we are determining the conversion architectures.


As you can see above when I have calculated the power required by the board I have performed two calculations the nominal and the maximum power, this is because at this point in time I have not calculated the maximum rail voltages provided in the worse case by the convertors therefore I have assumed they will be at maximum voltage. This is important as it is needed to determine the power required in the worse case by the AC/DC convertor (You should always design to address worse case requirements) while the difference above 146.5 mW is not large it could be in a larger system.

However having determined the load power we need to determine the overall power required including loses in the power convertors before we can specify the power required from the AC/DC convertor or DC Supply.

Having determined the power required by each device the next step is to determine the power required by each rail, this can then be used to determine the conversion architecture, although of course other requirements also come into play to determine this.

Regarding power architecture there are two main types of convertors

Switching regulators, generate the regulated output voltage by switching storage inductors into and out of the circuit to maintain a regulated output voltage when this switching is controlled via either an analogue or digital control loop. With a switching regulator theoretically 100% efficiency is achievable, however sadly the real world intervenes as components are not ideal however efficiencies greater than 90% can be achieved and GAN FET’s promise even better performance.

Linear Regulators generate the regulated voltage by dissipating the excess power across the pass transistor. This is dissipation is controlled via a control loop to adjust for fluctuations, as there is no switching involved the LR is often used where quieter power supplies are required however that does not mean all ripple on the voltage rail is rejected. As can be seen in the image below as the frequency increases the ripple rejection decreases.



Defining and Selecting Module Connectors


When designing any electronic system the modules connectors will have a significant impact upon the system reliability.

The system could be designed for a traditional high reliability application like railway, aerospace, medical, military or maybe an emerging one like high frequency trading.

Perhaps the first and simplest approach is to group the connectors in the functional types Power, Control, Data and Clocks etc. as each of these will be addressed in a different manner.

For instance it is possible to have prime and redundant power connectors, but if your system has a large number of data interfaces then it is not possible to have prime and redundant connectors for each input. This may lead to the need for system level redundancy in the worse case.

Regardless of the connector function we need to consider the following aspects

• Pin Derating, maximum reliability of a component is achieved by reducing the electrical stress placed upon it. There are many different standards for this (ESA, NASA, US Military etc) however; the basic idea is to reduce the voltage and current applied to the pins.

• Connector pin out, can a power pin short to a ground pin which will effect the overall power distribution system. It is therefore a good idea to ensure separation of power and ground separating them correctly. If necessary you can use unused pins to add isolation.

• Use of different connector types, styles and keying to prevent incorrect mating of connectors when the system is assembled. An incorrect assembly and power application could result in many hours of design analysis to prove no parts have been subject to electrical overstress.

• Number of mating cycles, the number of times the modules are mated / de-mated from the system has to be recorded. For this reason many designers use connector savers which can be connected to the system and reduce the number of mating cycles.

• Suitability for the job at hand for example if your system uses high speed serial links to communicate then your connector requirements will be very different from a power interface or low speed interface.

• Environmental and Dynamic considerations, many high reliability systems see extremes of temperature, vibration and shock. Can the connector system survive the demands and still stay connected.

Once you have determined your connector philosophy the next stage is ensuring you have a reliable system is in ensuring you cannot propagate a fault outside of your unit should a failure within occur.


Six Aspects to consider designing your PCB


pcbDesigning a PCB for current devices is a very complex and often over looked area instead focus falls upon the more interesting FPGA or Processors. However, the fact remains that without getting the board correct in the first place you may find you have issues either sooner or later so what are the main aspects of a modern PCB should we be concerned about.

  • PCB Stack up – the keystone of the entire PCB this defines the number of layers within the PCB (More layers can increase the cost) along with allowing the engineering team to establish the characteristic impedance on the required layers. This like many things in engineering becomes a trade-off between fabrication processes and layer count to achieve the reliability, yield and cost targets.
  • Via Types – Via’s enable interconnection between the layers and components however, there are many different types Through, Buried, Blind, and Micro (are these single layer, multi-layer or stacked). The best designs minimise the different types of via, close discussion with your selected PCB supplier is also important to ensure you’re via types are within their capabilities. You will also need to ensure the current carrying capacity of the different via types to ensure for high current paths you can parallel up.
  • Design Rules – These will address both rules for the design i.e. component placement, crosstalk budgets, layer allocation, length matching / time of flight analysis and so on. It will also include design for manufacture rules which ensure the finished design can actually be manufactured for instance are the via aspect rations correct.
  • Breakout strategy – before you can begin to verify your signal and power integrity you must first ensure you can break out and route all of the signals on high pin count devices. This will also affect the stack up of the PCB board for instance should you use micro via break out (most probably yes), how deep should these be is stacked micro via required. Once you have a defined stack for the PCB you can think of your routing strategy will it be the traditional North South East West, a layer based breakout or a hybrid style.
  • Signal Integrity – the most commonly considered aspects of designing a good PCB typically an engineer will consider aspect such as signal rise and fall times, track length and characteristic impedance, drive strength and slew rate of the driver and termination. To ensure the best performance SI simulations will be performed pre layout and post layout of the PCB, you will also need to consider the Cross talk budget.
  • Power Integrity – high performance devices especially modern FPGA and ASICs can require large currents at low voltages. Ensuring both the DC and AC performance of the power distribution network is of vital importance

Of course the list above is by no means complete however, it provides a good starting point


So We Just Consider the Resistor’s Tolerance Right?


When designing precision electronics or performing a detailed worst-case analysis, one quickly learns to consider parameters that may not be so important in other applications. One of the more interesting things to learn is that the tolerance of a resistor is just the starting point. It does not actually define the maximum or minimum value the resistor could be within your circuit.

The key parameters associated with a resistor are as follows.

Tolerance: This defines how close to the nominal value is allowable for the resistor when it is manufactured. A nominal 1,000Ω resistor with a tolerance of ±5% will have a value ranging between 950 and 1,050Ω. This value will be fixed; the value of the resistor will not vary during its life due to the tolerance. However, the engineer has to consider the tolerance in design calculations and ensure the circuit will function across the entire potential value range.

Temperature coefficient: This describes how the value of the resistor changes as a function of temperature. It is defined as parts per million/Kelvin; common values are 5, 10, 20, and 100 PPM/K. Actually, the best way to think of this is parts per million per ohm/Kelvin. A 1,000Ω resistor with a temperature coefficient of 100 PPM experiencing a ±60K temperature change over the operating temperature range (240-360K, based on an ambient room temperature of 300K) will experience a resistance change of ±6Ω based on its nominal value. Obviously, the lower the temperature coefficient, the more expensive the resistor will be. (This is the same for low-tolerance resistors.)


Resistor self-heating: For really high-precision circuits, it is sometimes necessary to consider the power dissipation within the resistor. The resistor will have a specified thermal resistance from the case to ambient, and this will be specified in °C/W. The engineer will know the power dissipation within the resistor; this can be used to determine the temperature rise and hence the effect on the resistance.
To determine the maximum and minimum resistance applicable to your resistor, you must consider the tolerance, the temperature coefficient, and the self-heating effect. As you perform your analysis, you may notice some of the parameters are negligible and can be discounted, but you have to consider them first to know whether or not you can discount them.

For some precision circuits (gain stages in amplifiers, for example) it may be necessary to match resistors to ensure their values are within a specified tolerance of each other and have the same temperature coefficients.

In certain circuits, it is also important to make sure that critical resistors are positioned correctly to ensure both terminal ends of the resistor are subjected to the same heating or cooling effects. Otherwise, the Seebeck effect may need to be considered. When using forced airflow, for example, it may be necessary to ensure that both resistor terminals are perpendicular to the airflow, so the component is of uniform temperature.


The Art of Decoupling


Like the perfect temperature at which beer should be served, the design and location of a decoupling capacitor network will return different answers depending upon who is being asked. The funny thing is that although the answers may be very different, each respondent will be sure that he or she is the only one who is correct.

Before I discuss my preferred beer-serving temperature and I explain how I design and locate my decoupling capacitors, I think it is important we all understand why we have decoupling capacitor networks in the first place. These networks are intended to perform two functions as follows:

  1. To provide a low impedance path to ground for AC signals and noise signals that are superimposed on the DC supply voltage.
  2. To act as a local energy store close to the device being decoupled such that high frequency demands for current due to logic gates switching, for example, can be supplied without the voltage rail being affected. (Remember that a power supply has a much slower response time to transient demands than the operational speed of the devices it powers. Indeed, at higher frequencies, on-chip decoupling is required, but that’s a story for another day.)

Both of these requirements will have bearing on the design of the decoupling capacitor network. We must also understand the parasitic elements and construction of a real-world capacitor, which — along with its capacitive element — will also have resistive and inductive elements as illustrated below:


Real structure of a capacitor (for decoupling purposes, RP is normally discounted).

Equivalent Series Resistance (ESR) is defined by the resistance of the leads or pads and losses in the dielectric; this is typically in the range of 0.01 to 0.1Ω for a ceramic capacitor.

Equivalent Series Inductance (ESL) is defined by internal connections or leads and pads. This is very important in the case of decoupling because it will dominate over the capacitance above certain frequencies.

From the model above, it is clear that the capacitor C and the ESL will form a series resonance creating a near short (it is not a dead short due to the ESR). You can calculate the Self Resonant Frequency (SRF) of a capacitor using the following equation:


What this means is that if you have a specific AC frequency you wish to remove, then you should ideally select a capacitor that has a SRF at the relevant frequency. Another consideration is to ensure a low impedance profile over a wide frequency band, which will require a range of capacitor values connected in parallel. For example, the network illustrated below employs two different value capacitors; observe the fact that there are more lower-value capacitors than higher-value capacitors


An example decoupling capacitor network.

When you are calculating this, do not forget the contribution of PCB inter-plane capacitance, which will dominate at high frequency. Inter-plane capacitance is achieved by careful design of the PCB stack to ensure that the power and ground planes are closely coupled within the stack, thereby creating capacitance.

It’s important to remember that the combined decoupling impedance is a function of all the different types and quantities of decoupling capacitors. The example below shows a combined decoupling capacitance (dark blue) formed by using 100nF capacitors (pink), 10nF capacitors (yellow), and 11µF capacitors (cyan/turquoise). In this case the combined decoupling impedance is required to be below 0.1Ω across a wide frequency range


Decoupling impedance, which is required to be below 0.1Ω across a wide frequency range.

Your target impedance will be defined by the parameters of the voltage supply being decoupled, the maximum transient current, and the allowable ripple on the rail as described by the following equation:


Having defined the target impedance, you can then use the capacitors available to you and their supplied information — capacitance, ESL, ESR, tolerance, and drift — to design a network that meets your impedance profile.

Your selection of decoupling capacitor will generally involve a ceramic device — commonly a multi-layer component — although polymer capacitors may be used for some applications. When it comes to selecting the most appropriate device, obviously you will start by looking for a low ESR and an acceptable SRF. You will also need to understand how the capacitor will operate across the desired temperature range and — more importantly — how the capacitance will change with temperature. For example, an X5R capacitor will work between -55 and +85°C with a change in capacitance of +/- 15% across the temperature range, while a Y7V capacitor will operate between -+30 and +125°C while exhibiting a variation of +22 to -82% of capacitance value — selecting the correct type is crucial.

Please remember to follow any recommendations made by the chip manufacturers also, because some devices have on-chip decoupling, which reduces the board-level decoupling requirements. The reasons for this will become clear in my next column in this miniseries.

Based on the discussions above, your decoupling network should now acknowledge the parasitic elements and component tolerances of the various capacitors you’ve selected. Sad to relate, however, this does not guarantee the final performance of the network. This is because we have not yet taken into account any parasitic parameters associated with the component mounting; nor have we considered the effects of component placement.

Whenever I talk to people about decoupling, they all say that the capacitor should be placed as close to the device as possible. However, very few people can actually tell me why this is and at what point “close enough” becomes “too far away.” As engineers, we need to understand what drives the placement of these components. Using this knowledge, we can define a series of rules regarding placement and layout such that the layout engineer is not simply just told to “put these as close as possible.” The lack of clear guidance can negatively impact the complexity of the design, the complexity of the manufacturing, and the cost of the circuit board.

A key aspect of decoupling is controlling the inductance associated with both the tracking and the mounting of the capacitor. Although the capacitor stores the charge, it is the inductance that determines the speed at which this charge can be delivered from the capacitor. Therefore, reducing the inductance loop is the most important aspect to consider when placing a capacitor.

This starts with the very design of the SMT (surface mount technology) capacitor mounting pads within your PCB library. Ideally the mounting via should be located as close as possible to the pad (though not within the pad unless you are using micro-via technology). If space permits, it is better to use multiple vias per pad as this reduces the overall inductance. You definitely do not want long thin tracks from the solder land to the via. Also, do not be tempted to share vias between capacitors.


The inductance loop is defined as being the loop created between the mounting via and the connections to the voltage planes. For this reason, when you define the stack of your board and assign layers to power and ground, you need to assign higher priority power planes (those with higher current demands from the device being decoupled) to be higher in the stack because this reduces the vertical distance the current needs to travel before reaching the plane.


When implemented correctly, the mounting inductance will be similar in value to the equivalent series inductance. This will have an impact on the resonant frequency (RF) of the capacitor, and hence should be included in the resonant frequency calculation. As the inductance increases, the resonant frequency — it is not the self-resonant frequency (SRF) as the mounting inductance is included — will be reduced:


Once calculated, the RF for the mounted component tells us the frequency at which the capacitor is most effective. Thus, we can use this to determine how close the capacitor needs to be located to the device it is decoupling so as to be most effective.

As the device being decoupled demands more current, it will cause a disturbance in the local power plane, and the decoupling capacitor will attempt to counteract this. There is a finite time between the device demanding current and the capacitor sensing and acting upon this demand. The time delay is calculated as follows:


You can determine the signal propagation speed in your circuit board by means of the following equation (where εr is the dialectic constant of the PCB material):


It obviously takes the same time delay for the current supplied from the capacitor to reach the device; hence, there is a “round trip delay.” We can therefore use the propagation speed “Vp” to determine the effective wavelength of the capacitor at its mounted resonant frequency. This wavelength can then be used to determine how close to the device being decoupled the capacitor needs to be placed using the following rules:

  • When the capacitor is located more than a quarter of a wavelength away, the capacitor has no effect on the device being decoupled.
  • The energy transfer will increase the closer the capacitor is located to the device being decoupled.
  • An ideal target is to place capacitors within 1/40th of a wavelength. This means that smaller value capacitors have to be placed closer than do larger ones.

You can calculate the wavelength of the capacitor using the following equation:


As was noted above, it’s good practice to locate the decoupling capacitors within 1/40th of the wavelength, which means you will have zones of decoupling as shown below:


Priority should be given to termination resistors and discrete filtering capacitors for things like high-speed serial link power supplies over decoupling capacitors close to the device.

So now we understand the reasons why we decouple and how we go about doing this on the final design, including the rules outlining the placement of our decoupling capacitors. It is possible to verify the final layout using tools like HyperLynx Power Integrity from Mentor Graphics, which will not only look at DC drops across planes (this is just as important as decoupling) but also the AC performance