Mission Critical Course

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Workshop – Developing for Mission Critical FPGA & SoC

FPGA’s and heterogeneous SoC’s are used in an increasing number of mission critical or high reliability applications. These applications span a diverse range from industrial, medical and scientific to defences, transportation and even space. For these devices to safely and reliability operate in an often-harsh environment, a more rigorous design approach is required. One that introduces both stricter engineering governance in the design process and design mitigation techniques

As such designing these solutions requires the designer to not only understand what techniques can be used at the logic level but also, the wider systematic, regulatory and environmental issues.
This course will therefore present the environmental challenges and what they mean to the logic designer. Along with introducing high level concepts such as SIL level, Reliability and Mean Time to Failure, attendees will also gain an understanding of the importance of engineering governance.

The focus of this course is the development of techniques which can be used in programmable logic including Clocking & Reset strategy, Triple Modular Redundancy, IO Planning, Safe State Machines and Counters, Error Correcting Codes, Single Event Effect Mitigation along with Verification strategies and metrics, formal equivalence checking, Synthesis strategies and several other advanced techniques.

Each session will complete with a Lab which will demonstrate the concepts outlined in the session. Attendees will at the completion of the course have a detailed understanding of the challenges and strategies to address the creation of mission critical systems for a wide range of applications.

Agenda

  • How the environment impacts our designs
  • Temperature, Shock & Vibration, EMC and Radiation
  • Programmatic / System level considerations.
  • Different Standards 61508 / DO254 / ISO 26262
  • The design life cycles
  • Engineering Governance
  • What is reliability & What does MTBF Mean & What impacts the MTBF
  • Requirement capture & Progressive Verification
  • Architectural design & Inter dependency of faults between SW and HW
  • Common Cause Failures & Failure Mode & Redundancy
  • Worse Case Analysis
  • FPGA Design Considerations
  • FPGA Development overview & Supporting Documentation
  • Device Selection – OTP, FLASH, SRAM
  • Coding Style & Certified tools
  • Failure modes
  • Self-Test and Diagnostics
  • Clocks and Rest & IO Planning & JTAG / Boundary Scan
  • Safer State Machines & Counters
  • Error Correcting Codes Communications and Memories
  • Triple Modular Redundancy Local, Fine Gain and Global
  • Functional Separation within the device, Isolation flow
  • Single Event Effects and Configuration Corruption
  • Verification & Verification Metrics
  • Fault Injection
  • Timing Closure
  • Advanced Features e.g. XADC, SysMon,

Duration: – 2.5 Days

Applicable Technologies: – These techniques outlined in this course can be applied to any FPGA technology. For reference course Xilinx Seven Series devices will be targeted.

Requirements: – It is expected that the attendee is an experienced FPGA designer and has familiarity with electronics and system engineering concepts.

If want to know more for examples locations, dates and pricing please contact me 

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