One thing that is always important for engineers, is the need for us to deliver our projects on quality, schedule and budget. When it comes to developing embedded systems there are a number of lessons, learnt by embedded system developers over the years which can be used to ensure your embedded system achieves these. Let us explore some of the most important lessons learned in developing these.
Slides presented at ESC Minn 2015 on aspects to consider when creating a embedded system.
Three things to consider for your prototyping
One of the most exciting stages of an engineering project is when the hardware arrives in the lab for the first time ready for commissioning before integration testing. This typically can mean long hours for all the engineers on the project so how can we try and reduce this time and minimize the issues which may arise.
- Think how you will test it from day one – All engineers know the cost of implementing fixes increases as the development progresses. It is more expensive to fix a pin out error once the design has been fixed and manufactured than during an early design review for example. This is the same for testing, thinking of how you will test it from day one and what test equipment you might need.
- Think about what to include in the design – During the design of the hardware several design features and functions may need to be included to allow testing of the board with greater ease. The most simple and often implemented test provision is placing test points on all voltage rails Being able to monitor the outputs of clocks and resets is also important, for this reason it is good practice to place test points on the reset line and correctly terminate an unused clock buffer and add test points allowing the clock to be probed with ease. Many modern high performance devices also have on die temperature diodes which can be used during your testing to determine the junction temperature of the die is acceptable, provided you can access these points.
- Simple RTL – If you have a complicated design at both the hardware and FPGA level it can be best to develop a more simplified cut down version of the RTL to aid in the testing of the board and the interface between the FPGA and the peripheral. This is especially the case if you are designing high speed interfaces. This cut down RTL could be used in conjunction with chip scope to capture data and block rams which have been pre loaded with data patterns to act as stimulus. This can especially be the case when using ADCs and DACs connected to a FPGA the reprogrammable nature of the FPGA should be utilized to the maximum to develop designs which will allow parametric testing of the ADC and DAC for instance Noise Power Ratio, Spurious Free Dynamic Range and effective number of bit calculations. You should also aim to capitalize on the resources provided by the FPGA especially system monitor and XADC which can be very useful for monitoring the voltage rails on die and hence helping verify the power integrity analysis
What if it does not go to plan? The first thing to do is not panic, for many issues you will probably not be the first person to face this issue(s) though it may feel like it. Revisit the design schematics, layout and read the data sheets and any errata’s again also have a look on some of the very helpful websites like All Programmable Planet or the Xilinx Forums there are plenty of helpful ones out there.
One the most exciting, fun and terrifying stages of engineering is when the first prototypes or engineering models arrive in the lab and are ready for testing. You will have been planning for this day for a long time (hopefully) as the cost of identifying and correcting errors later on in the production run only increases.
Planning for this day will have started right back at the concept of the design as you considered how you would test the functionality being designed into the hardware, FPGA and processors etc. Ensuring you have provided sufficient test points and protected them appropriately (you would hate to short out a rail as you tried to measure the voltage). One thing you also need to consider is accessibility of these test points and debug headers to ensure you can actually access them. Another aspect to consider is how you can test the board on its own will you need any special to type test equipment to enable you to test it, when will it be available.
You will also need to compile a test plan to detail everything you intend to test and the expected results otherwise how else can you be expected to know if performs as required or not.
Once you get the hardware in the lab the testing is generally split into two sections the section is checking the hardware integrity i.e. can it be powered on safely and is it suitable for further testing. During this stage you will check the board has been manufactured and populated correctly, that the voltage rails are safe to turn on and then will come the moment of truth when you have to apply power to the board for the first time. This is always a nerve wracking moment…
Once you have applied power you will be looking at the current drawn against your projections, are the clocks at the correct frequency, does the protection circuitry (over voltage / under voltage) resets and sequencing function as desired. This is the basic engineering tests that will be your first priority however; you will soon progress to wanting to test the more complex interfaces and then the performance.
Some of these may be able to be tested via JTAG / Boundary scan however it is only really testing at speed that you can relax a little (you can never truly relax even after all the qualification testing) It is therefore a great idea to have developed some simple test code for your FPGA or microprocessor to prevent you having to debug both the FPGA/Microprocessor design and the board design. I am sure we have all spent many hours looking into is the issue with the board, FPGA, processor or even worse the ASIC.
Once you have completed the integrity checks you can then proceed to testing the functionality and working out what changes you need to make to the next iteration if any.
Of course at some point I am sure you will encounter problems the most important thing to remember at that point is to not panic and attempt to determine the root cause of the issue even if there is nothing you can do about it on the prototype.
One of the more interesting aspects to start looking at is the power architecture of a design, and how we go about powering FPGA’s (and other devices) on the board. Normally the system will have an intermediate voltage which comes from an AC/DC convertor or other DC supply which powers the system. The first stage of the design is to correctly specify this interface in terms of voltage and current required by the design. Determining this intermediate voltage is the easier task of the two, as the current required will have to take into account the downstream convertor efficiencies.
The first stage in defining power architecture is the determination of all the voltage rails and currents drawn by each of these rails. For example when considering a FPGA based imaging system as shown below you may have a number of voltage rails
For this example all of the power supplies have a requirement to be within +/-5%.
As can be seen from the table above the highest voltage required is 3.465V which is the 3.3V at its maximum acceptable tolerance. Knowing this value allows us to determine the voltage supplied by the AC/DC or other DC supply within the system, the sensible thing to do here is to select a convertor which has an output compatible with the 3.3V required and save a conversion stage (increasing the overall efficiency).
The next stage is to determine the power required by each of the rails. The requires that you use power estimation tools such as Xilinx XPE and read the datasheets for other devices to ensure you can determine the power required, I tend to collate all of this in a spread sheet as this comes in useful later on once we are determining the conversion architectures.
As you can see above when I have calculated the power required by the board I have performed two calculations the nominal and the maximum power, this is because at this point in time I have not calculated the maximum rail voltages provided in the worse case by the convertors therefore I have assumed they will be at maximum voltage. This is important as it is needed to determine the power required in the worse case by the AC/DC convertor (You should always design to address worse case requirements) while the difference above 146.5 mW is not large it could be in a larger system.
However having determined the load power we need to determine the overall power required including loses in the power convertors before we can specify the power required from the AC/DC convertor or DC Supply.
Having determined the power required by each device the next step is to determine the power required by each rail, this can then be used to determine the conversion architecture, although of course other requirements also come into play to determine this.
Switching regulators, generate the regulated output voltage by switching storage inductors into and out of the circuit to maintain a regulated output voltage when this switching is controlled via either an analogue or digital control loop. With a switching regulator theoretically 100% efficiency is achievable, however sadly the real world intervenes as components are not ideal however efficiencies greater than 90% can be achieved and GAN FET’s promise even better performance.
Linear Regulators generate the regulated voltage by dissipating the excess power across the pass transistor. This is dissipation is controlled via a control loop to adjust for fluctuations, as there is no switching involved the LR is often used where quieter power supplies are required however that does not mean all ripple on the voltage rail is rejected. As can be seen in the image below as the frequency increases the ripple rejection decreases.
When designing any electronic system the modules connectors will have a significant impact upon the system reliability.
The system could be designed for a traditional high reliability application like railway, aerospace, medical, military or maybe an emerging one like high frequency trading.
Perhaps the first and simplest approach is to group the connectors in the functional types Power, Control, Data and Clocks etc. as each of these will be addressed in a different manner.
For instance it is possible to have prime and redundant power connectors, but if your system has a large number of data interfaces then it is not possible to have prime and redundant connectors for each input. This may lead to the need for system level redundancy in the worse case.
Regardless of the connector function we need to consider the following aspects
• Pin Derating, maximum reliability of a component is achieved by reducing the electrical stress placed upon it. There are many different standards for this (ESA, NASA, US Military etc) however; the basic idea is to reduce the voltage and current applied to the pins.
• Connector pin out, can a power pin short to a ground pin which will effect the overall power distribution system. It is therefore a good idea to ensure separation of power and ground separating them correctly. If necessary you can use unused pins to add isolation.
• Use of different connector types, styles and keying to prevent incorrect mating of connectors when the system is assembled. An incorrect assembly and power application could result in many hours of design analysis to prove no parts have been subject to electrical overstress.
• Number of mating cycles, the number of times the modules are mated / de-mated from the system has to be recorded. For this reason many designers use connector savers which can be connected to the system and reduce the number of mating cycles.
• Suitability for the job at hand for example if your system uses high speed serial links to communicate then your connector requirements will be very different from a power interface or low speed interface.
• Environmental and Dynamic considerations, many high reliability systems see extremes of temperature, vibration and shock. Can the connector system survive the demands and still stay connected.
Once you have determined your connector philosophy the next stage is ensuring you have a reliable system is in ensuring you cannot propagate a fault outside of your unit should a failure within occur.
Designing a PCB for current devices is a very complex and often over looked area instead focus falls upon the more interesting FPGA or Processors. However, the fact remains that without getting the board correct in the first place you may find you have issues either sooner or later so what are the main aspects of a modern PCB should we be concerned about.
- PCB Stack up – the keystone of the entire PCB this defines the number of layers within the PCB (More layers can increase the cost) along with allowing the engineering team to establish the characteristic impedance on the required layers. This like many things in engineering becomes a trade-off between fabrication processes and layer count to achieve the reliability, yield and cost targets.
- Via Types – Via’s enable interconnection between the layers and components however, there are many different types Through, Buried, Blind, and Micro (are these single layer, multi-layer or stacked). The best designs minimise the different types of via, close discussion with your selected PCB supplier is also important to ensure you’re via types are within their capabilities. You will also need to ensure the current carrying capacity of the different via types to ensure for high current paths you can parallel up.
- Design Rules – These will address both rules for the design i.e. component placement, crosstalk budgets, layer allocation, length matching / time of flight analysis and so on. It will also include design for manufacture rules which ensure the finished design can actually be manufactured for instance are the via aspect rations correct.
- Breakout strategy – before you can begin to verify your signal and power integrity you must first ensure you can break out and route all of the signals on high pin count devices. This will also affect the stack up of the PCB board for instance should you use micro via break out (most probably yes), how deep should these be is stacked micro via required. Once you have a defined stack for the PCB you can think of your routing strategy will it be the traditional North South East West, a layer based breakout or a hybrid style.
- Signal Integrity – the most commonly considered aspects of designing a good PCB typically an engineer will consider aspect such as signal rise and fall times, track length and characteristic impedance, drive strength and slew rate of the driver and termination. To ensure the best performance SI simulations will be performed pre layout and post layout of the PCB, you will also need to consider the Cross talk budget.
- Power Integrity – high performance devices especially modern FPGA and ASICs can require large currents at low voltages. Ensuring both the DC and AC performance of the power distribution network is of vital importance
Of course the list above is by no means complete however, it provides a good starting point
Safety-critical systems nowadays include more and
more embedded computer systems, based on different hardware
platforms. These hardware platforms, reaching from microcontrollers
to programmable logic devices, lead to fundamental
differences in design. Major differences result from different
hardware architectures and their robustness and reliability as
well as from differences in the corresponding software design.
This paper gives an overview on how these hardware platforms
differ with respect to fault handling possibilities as fault avoidance
and fault tolerance and the resulting influence on the safety
of the overall system.
From the functionality point of view, FPGAs became
very interesting for industrial applications. Reasons are the
constantly decreasing costs of microelectronics and improvements
in the corresponding design tools as well as the increasing need
of complex real-time functionalities in these applications. However,
other non-functional requirements have to be considered.
Therefore, the potentials of FPGAs for industrial applications
are considered in this paper on basis of hardware attributes
representing the contribution of these systems to system qualities
as for example performance, reliability and marketability.
This paper describes a proposal for a
space flight demonstration of a low
power, compact Dynamically
Reconfigurable Programmable Board
(DRPB) based upon a minor evolution
of the Astrium Janus payload for
A PROPOSAL FOR A SPACE FLIGHT DEMONSTRATION OF A DYNAMICALLY RECONFIGURABLE
PROGRAMMABLE MODULE WHICH USES FIRMWARE TO REALISE AN ASTRIUM PATENTED COSMIC
RANDOM NUMBER GENERATOR FOR GENERATING SECURE CRYPTOGRAPHIC KEYS