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Security is becoming increasingly important in many of the FPGA applications we develop, several talks at the recent FPGA Horizons London focused on this. Whether we are working on communications, industrial, automotive or space systems, our devices are increasingly connected, and the world in which they are deployed is a much more hostile place than it once was, as demonstrated over the last week with several cyber attacks on established frameworks. Of course, it is not jus

I spend a lot of time reading forums and social media related to FPGA. Recently I was reading r/fpga and saw some interesting interview questions someone had been asked at a finance company. There were two questions. 1. You have a 100 MHz reference clock and another clock with an unknown frequency. Design a circuit to measure the unknown frequency. 2. Given a one cycle input pulse, generate an output that stays high for ten clock cycles in total, the input cycle plus nine mor

Back when I first started writing this blog in October 2013, I would never have imagined we would be able to leverage AI to develop a significant element of the FPGA / SoC creation process. However, as the devices and tools have evolved, so too have the capabilities of AI over the last few years, and we are now able to significantly accelerate our designs if we understand FPGA development. Having looked recently at AI code generation, I was going to focus on other FPGA-relate

Yesterday marked the second FPGA Horizons London, held at the Pullman Hotel, and what an incredible event it was. Having turned away nearly 200 people when I ran the first event last year, I decided to be a little more ambitious this time and booked the entire facility, including the Shaw Theatre, which seats 450 people. To put that into perspective, FPGA Horizons London 2025 attracted 290 attendees, 28 exhibitors and 21 speakers. Looking around the venue again yesterday, I a

FPGA Horizons London- October 6th and 7th 2026 - get Tickets here. The $99 Artix UltraScale+ Explorer Board - learn more here Last week we looked at whether a language model running entirely on a machine on my desk could generate RTL that compiles. The short answer was yes, with the caveat that a compile pass means the code parses and elaborates and nothing more or as one comment on linkedin put it “It compiles, so let's ship it!! Exactly my sense of humour” That of course wa

FPGA Horizons London- October 6th and 7th 2026 - get Tickets here. The $99 Artix UltraScale+ Explorer Board - learn more here One of the questions I get asked the most at the minute is whether AI can actually help us with our RTL development. I have spoken several times about how frontier models can help us, and how our role as engineers is evolving as we are able to leverage higher levels of abstraction. However, while frontier models are excellent, for many of us working in

FPGA Horizons London- October 6th and 7th 2026 - get Tickets here. The $99 Artix UltraScale+ Explorer Board - learn more here In my last blog, I introduced a debug laboratory: a Spartan-7 design that can be deliberately broken. It allows us to select one of six realistic faults at run time and then find them using ILA cores inserted into the design. In this blog, we are going to look not only at running the experiments on hardware, but also at identifying the key characterist

FPGA Horizons London- October 6th and 7th 2026 - get Tickets here. The $99 Artix UltraScale+ Explorer Board - learn more here Over the years of writing this blog, most of the designs we have created have one thing in common: they work - well, after a while. Of course, getting them working often involves debugging on the hardware, just as many real-world projects do. By the time the blog is published, however, the issues have been found and fixed. It is good that they work, as

FPGA Horizons London- October 6th and 7th 2026 - get Tickets here. The $99 Artix UltraScale+ Explorer Board - learn more here FPGAs are widely used in image-processing applications across automotive, robotics, industrial, defence, and scientific systems. Their ability to process large amounts of data in parallel makes them particularly well suited to real-time image-processing pipelines. However, image sensors are not perfect. They can contain dead or unresponsive pixels, pix

FPGA Horizons London- October 6th and 7th 2026 - get Tickets here. The $99 Artix UltraScale+ Explorer Board - learn more here This week I have been helping a couple of clients with FPGA projects that were not going quite as hoped. While I am not going to explain the exact issues they faced, it did remind me of a few different elements of FPGA design and their importance. Lesson 1: Do not leave FPGA inputs floating The first project was a custom-designed board that was not fun

FPGA Horizons London- October 6th and 7th 2026 - get Tickets here. The $99 Artix UltraScale+ Explorer Board - learn more here I think, for the good of my bank account and my accountant’s sanity, I am going to have to block Crowd Supply on my company network. Last week, another item I had ordered, and might have forgotten about arrived, the xSDR. The xSDR is based around an Artix-7 FPGA coupled with a Lime Microsystems RFIC and is implemented in a compact M.2 format. For ease

FPGA Horizons London- October 6th and 7th 2026 - get Tickets here. The $99 Artix UltraScale+ Explorer Board - learn more here Just over a year ago I wrote a blog which pulled together the DSP resources I had created over the years, covering the foundations such as fixed and floating point maths, rounding, the CORDIC algorithm, working with ADCs and DACs, and an introduction to filters and the frequency domain. Since then, driven largely by the DSP for FPGA course I have been

FPGA Horizons London- October 6th and 7th 2026 - get Tickets here. The $99 Artix UltraScale+ Explorer Board - learn more here One of the more ambitious decisions we made on the Adiuvo Explorer board was to bring out the Artix UltraScale+ GTH transceivers. As I have explained several times one of the motivations behind the explorer board is to demonstrate we can create an effective 0.5 mm pitch BGA PCB using only through hole vias. We have achieved this using an offset via tec

FPGA Horizons London- October 6th and 7th 2026 - get Tickets here. The $99 Artix UltraScale+ Explorer Board - learn more here Over the last few blogs we have been looking at element of DSP and signal processing, especially elements which allow us to work in the frequency domain such as Filters and Fourier Transforms. I have also been experimenting a little recently with the Opal Kelly XEM7320,and FrontPanel which is very interesting for visualisation. So using the XEM7320 fit

FPGA Horizons London- October 6th and 7th 2026 - get Tickets here. The $99 Artix UltraScale+ Explorer Board - learn more here Over the last few weeks we have looked at some of the basics of DSP in FPGA, from filters such as FIR and IIR to DFT and FFT. Continuing this exploration of basic DSP elements there is a common challenge we often face in DSP, that is changing the sample rate of a signal. Example of the need to change the sample rate include working with a delta-sigma m

FPGA Horizons London- October 6th and 7th 2026 - get Tickets here. The $99 Artix UltraScale+ Explorer Board - learn more here One of the things I've always enjoyed over the years is sharing my passion for FPGA design, whether that's through blogs, projects, or demonstrations showing how to build FPGA-based solutions. Since I started, the FPGA Horizons Journal it has become increasingly popular and attracted some excellent articles covering a wide range of FPGA technologies an

FPGA Horizons London- October 6th and 7th 2026 - get Tickets here. The $99 Artix UltraScale+ Explorer Board - learn more here Over the last few weeks, whenever I have had some spare time, I have been bringing up the Explorer board. So far, most of the board is up and running, and the signal integrity measurements appear to be aligning with our expectations. I will talk more about this later once we have completed our analysis. However, one of the things I have wanted to do fo

FPGA Horizons London- October 6th and 7th 2026 - get Tickets here. The $99 Artix UltraScale+ Explorer Board - learn more here A few weeks ago, I had the privilege of giving the keynote at the CERN FPGA Developers Conference. It was a fantastic event, bringing together engineers from across industry and research. For my keynote, I wanted to be informative, inspirational, and perhaps a little challenging. Long-term readers will know that I am a strong advocate for systems engin

FPGA Horizons London- October 6th and 7th 2026 - get Tickets here. The $99 Artix UltraScale+ Explorer Board - learn more here Along our journey exploring algorithms from first principles, we have previously looked at the DFT, FFT, and polynomial approximation. Continuing this exploration, another very useful technique often implemented within FPGA designs is linear interpolation. Linear interpolation is used to estimate an unknown value between two known data points by assumi

FPGA Horizons London- October 6th and 7th 2026 - get Tickets here. The $99 Artix UltraScale+ Explorer Board - learn more here A few weeks ago we looked at implementing a DFT from scratch as part of the labs for the DSP for FPGA course I am developing. The DFT worked nicely; however, we finished by noting that it does not scale well. For a DFT of size N, we need N² complex multiplications, which means a 1024-point DFT requires over a million of them. This is where the Fast Fou