In this post, we will expand the use of GHDL with an open-source verification framework for VHDL called UVVM.

In this blog let's look at how to install GHDL and use it to simulate our VHDL designs.

Silexica has released a plugin for Vitis HLS 2020.2 that adds a new pragma that performs loop interchange.

I thought I would examine how we can implement safe state machines when using Vivado 2020.2 and Xilinx synthesis

The Trenz ZynqBerry Zero is in the same form factor as the Raspberry Pi Zero, but with a Zynq Z-7010. Let's take a closer look.

I need an entry-level scope for a project I am working on so I decided I would pick up a Tektronix TBS1052C and take look at what is inside.

One of the most useful views available in both Vivado HLS and Vitis HLS is the analysis view.

This past summer, I was lucky to present several detailed virtual workshops on Vivado, PYNQ, Vitis, and more. They are available on-demand.

The AXI Stream VIP is extremely useful when we want to generate signal and image processing IP that use AXI Stream for interfacing.

The designs we implement in Vivado often use AXI interfaces. These might be AXI Lite for configuration and control, AXI Memory Mapped

I recently received the new Trenz TE0802 development board, designed and manufactured by Digilent partner Trenz Electronic.

For complex algorithms, it is often a good idea to first create a model which defines the algorithm’s behavior.

No matter how captured (RTL, HLS, Model Driven), all programmable logic designs should start with agreed requirements that define the...

So, before we look in more detail at Vivado XSIM, let’s first understand the entire verification landscape and what we are trying to achieve

Using Xilinx UltraFast design methodologies can offer significant benefits when implementing designs.

In this blog we explore the Quality of Result Assessment (QoRA) and Quality of Result Suggestions (QoRS).

One of the most time-consuming elements of implementing an FPGA design is not often the design capture, but achieving timing performance.

This is a follow-on to last week’s demonstration of developing embedded software using Vitis 2020.1. In this week’s blog, we are going to...

In the last blog, we looked at how we could start to create a MicroZed project in Vivado 2020.1 just like we did when we started the blog...

When I started this blog nearly seven years ago now, we developed the solution in Vivado 2013.2. Following that, we have gone on to examine