One of the main methods of increasing timing performance in our FPGA designs is to implement pipelining. At its heart, pipelining allows...

I am often asked in emails and social media such as LinkedIn / (X) Twitter, what projects people learning FPGA should look at that are...

FPGA are excellent for image processing, their parallel nature easily allows us to implement parallel processing stages. Over the years...

XADC as part of a temperature reporting system which allowed me to demonstrate the power of using a model based approach. One of the...

Regular readers will know I am big fan of the System of Module approach,  we design many into systems and solution for out clients and if...

One of things which helps us accelerate our development times is to leverage model based development. This enables us to work at a higher...

Over a Over a series of blogs we have been exploring the Alveo V80 board, the Alveo Versal Example Design (AVED) its constituent parts...

FPGAs are commonly used across a range of applications from Space, and Aerospace to Automotive, Robotics, and Commercial applications....

So far on our journey of exploring the Alveo V80 we have examined the hardware and software elements necessary for creating the AVED...

Last week we examined how we could work with Git and source control on our FPGA designs. Along with working with Git for source control,...

One of the skills which FPGA developers need to master is that of working with source control tools such as git. A few months ago I...

One of the things I love about all AMD FPGA and SoC devices is the inclusion of the XADC / Sysmon ADC. This allows us to monitor not only...

Over the years, I have worked on a range of engineering projects in various roles, from being the FPGA engineer, hardware engineer to the...

One of the major differences with the Alveo V80 accelerator card is the implementation of the satellite controller. The satellite...

Last week, we examined the new MicroBlaze V, which is based on the popular RISC-V RV32I Instruction Set Architecture. This enabled me to...

One of the things I have been very excited about recently is the MicroBlaze RISC-V or MicroBlaze V as it will be known.  The MicroBlaze V...

Last week, we looked at how we could create a baseline timing closure, which hopefully helps with achieving timing closure. Of course,...

In our first blog and introduction to the new Alveo V80, we examined the features and capabilities of the board itself. In this blog we...

There are many factors that come together to create a successful FPGA design. Not only do we need to have a sensible architecture, IP...

One of the tasks I have been meaning to accomplish since receiving the Avnet ZU1CG board is connecting the high-speed IO interface with...