For many applications, selecting the most appropriate device is critical. Many of our clients are often questioning which device they...

Last week we examined how we could create a UART with AXI Stream interfaces to enable access to AXI buses in device for debugging. In...

Introduction As part of our ongoing series of blog posts on high-speed serial transceivers we are going to look at how to create a...

A few weeks ago, we examined how we could create the hardware element of a RISC-V processor using Lattices Propel tool. The culmination...

As we know, FPGA design and FPGA verification are complex businesses. Then, of course, comes integration, at which time the actual...

Several times in recent blogs and posts on LinkedIn and Twitter I have mentioned that at Adiuvo we use a lot of RPI Pico’s for hardware...

Last week we looked at configuring and deploying multi-gigabit GTH transceivers using the GTH wizard. One of the key things when using...

Introduction It is a common problem in FPGA design to have to send high-bandwidth data (such as video) between two different FPGAs. ...

A few months ago, we looked at GitHub Copilot. The tool uses AI to assist with the coding process and it felt a little like pair...

We looked recently at the UltraScale+ IO resources which provide a range of capabilities that can be very effective in addressing both...

Model-based engineering enables engineers to cut down development times by a factor of 5 while maintaining the highest levels of quality.

One of the great features about the new Avnet ZU1CG board is the interfacing it provides. It gives us three SYZYGY interfaces along with...

One of my passions is sharing information about how we can develop better, more effective FPGA designs. This passion is the driving force...

A few months ago, we looked at the AXI Stream FIFO. The AXI Steaming FIFO allows developers to be able to access AXI Streams from AXI...

Announcing 3 new FPGA development-related courses, including a basics course targeted at new graduates or entry-level engineers.

Over the last few weeks, I have been working on commissioning the Nexus Certus™-NX LFD2NX-40 development board. You can find a previous...

It is always exciting when new devices are introduced, and this week, AMD Xilinx announced two new devices into the already popular Artix...

It’s common for many custom FPGA board developments to contain a DDR3 memory. Of course, when we develop a custom board, we need to...

Last week we examined the Video Frame Buffer Write (VFBW), which is capable of writing image frames to an external memory. This week, we...

When I’ve previously created image processing blogs or applications, I have tended to use the Video Direct Memory Access (VDMA) module to...