The announcement earlier this year on the collaboration between CAES and Lattice Semiconductor on the availability of space grade...

A few days ago, I noticed that AMD Xilinx had published a blog stating that 7 series devices would be available beyond 2035. I must admit...

On my journey exploring how Cocotb works on a range of interfaces, this week I am going to look at how we can work with AXI Lite and...

A few weeks ago, we looked at how we could build the hardware element of our Nios V processor using Quartus Prime and Platform Designer....

Over the last few weeks, I have been creating a course centered around the Avnet ZUBoard which will be like the MiniZed and Ultra96-V2...

A few weeks ago, we looked at the python-based cocotb framework. In that blog, we looked at a simple memory scrubber created around a XPM...

In our last blog, we looked at the new Nios V soft-core processor for use in our Intel FPGAs. In this blog, we are going to explore how...

Ever since the previous overview, I’ve had the Avnet ZUBoard 1CG sitting on my desk. I also just purchased a FLIR C5 thermal imaging...

Verification of both the modules and top-level testing is often more complex and time consuming than creating the HDL. Previously, we’ve...

A few weeks ago, we talked about how we could synchronise between clock domains in Vivado, I also noticed a couple of questions on r/FPGA...

One of the great things about the BRAM in Xilinx FPGAs is its ability to implement error correcting codes (ECC) on the data stored...

A few weeks ago, we looked at took a high-level view of the open-source tools which are combined to create the Rapid Silicon Raptor tool...

Writing good, portable, reusable HDL code, that enables the synthesized design to implement at the desired frequency can definitely be a...

When I started my design career twenty plus years ago, one of the very simple rules we had for significantly smaller and less flexible...

A couple of weeks ago, I mentioned I had invested in MATLAB and HDL Coder to enable generation of RTL code directly from Simulink models....

In early June Avnet announced the ZUBoard 1CG, as a compliment to the Ultra96V2 and MiniZed development boards and UltraZed and PicoZed...

One of the game changing elements of the announcement from Rapid Silicon was that the entire tool chain would be based on open-source...

I have recently come across an interesting requirement from a customer that includes driving high-energy systems with a series of pulses...

We looked at the Agilex Transceiver-SoC Development Board in the last blog. Besides the great capability of this board, one of the main...

Last week, after we looked at how we could use the AXI IIC IP with PYNQ, I got a question from a reader asking how we work with...