clocking | Adiuvo Engineering

ADIUVO ENGINEERING BLOG

Oct 304 min read

MicroZed Chronicles: Synchronous CDC

Every digital / FPGA designer should be aware of clock domain crossing between asynchronous clock domains. As our devices get more and...

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Sep 27, 20233 min read

MicroZed Chronicles: Outputting Clocks

We all know that if we want to get the best performance, we should place input clocks to our FPGAs on clock capable or dedicated clock...

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Jul 18, 20233 min read

MicroZed Chronicles: Versal Clocking Resources

Over the last few weeks, we have looked at some interesting aspects of the 7 series and UltraScale / UltraScale+ clocking buffers. To...

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Jul 11, 20234 min read

MicroZed Chronicles: UltraScale and UltraScale+ Clock Division

Last week we looked at how we could use 7 series clocking resources to provide integer clock division without using MMCM. In this week’s...

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Jul 5, 20233 min read

MicroZed Chronicles: Clock Structures and Clock Division

Many of our FPGA designs are multi-clock, meaning several clocks within the design, which can introduce clock domain crossing challenges....

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May 17, 20233 min read

MicroZed Chronicles: Dynamic Clocking

Clocking is at the heart of every FPGA design.. We can spend a lot less time battling the tools if we get the clock architecture right,...

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Aug 16, 20223 min read

MicroZed Chronicles: Thinking about Clocks.

When I started my design career twenty plus years ago, one of the very simple rules we had for significantly smaller and less flexible...

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