In this blog, we often talk about detailed design features or aspects of FPGA or heterogeneous SoC design. This allows us to learn about...

There is a wide range of development boards on the market today. Some are ideal for beginners who are just learning programmable logic or...

Along side FPGA development I am also interested in Microprocessors, especially those which can be used for edge applications. A few...

We looked at fixed point math a few weeks ago and we’ve also previously looked at how we can use DSP48 in both 7 series and UltraScale+...

Our programmable logic designs are often deployed in applications which can be electrically noisy. This noise can affect the signals that...

Lately we have been discussing helpful tips and tricks, the best development boards and even the best books to reference if you’re...

One of the questions I get asked a lot is which development board is the best for (beginner) FPGA and SOC development. Understandably,...

A lot of my FPGA development takes place within Visual Studio Code where I use it with TerosHDL to create HDL and cocotb for...

We often use finite state machines (FSM) when we want to implement control structures in our programmable logic structures. As complexity...

Over the last few weeks, we have been working to create a simple system which allows debugging from a UART into an AXI Lite network. This...

Last week we examined how we could create a UART with AXI Stream interfaces to enable access to AXI buses in device for debugging. In...

A few weeks ago, we examined how we could create the hardware element of a RISC-V processor using Lattices Propel tool. The culmination...

Several times in recent blogs and posts on LinkedIn and Twitter I have mentioned that at Adiuvo we use a lot of RPI Pico’s for hardware...

We looked recently at the UltraScale+ IO resources which provide a range of capabilities that can be very effective in addressing both...

One of my passions is sharing information about how we can develop better, more effective FPGA designs. This passion is the driving force...

It’s common for many custom FPGA board developments to contain a DDR3 memory. Of course, when we develop a custom board, we need to...

The announcement earlier this year on the collaboration between CAES and Lattice Semiconductor on the availability of space grade...

A few weeks ago, we looked at how we could build the hardware element of our Nios V processor using Quartus Prime and Platform Designer....

A few weeks ago, we looked at the python-based cocotb framework. In that blog, we looked at a simple memory scrubber created around a XPM...

In our last blog, we looked at the new Nios V soft-core processor for use in our Intel FPGAs. In this blog, we are going to explore how...