Coral Micro Dev Board
Along side FPGA development I am also interested in Microprocessors, especially those which can be used for edge applications. A few...
top of page
ADIUVO ENGINEERING BLOG
Search
Adam Taylor
Apr 19, 20233 min read
MicroZed Chronicles: A look at the DSP58
We looked at fixed point math a few weeks ago and we’ve also previously looked at how we can use DSP48 in both 7 series and UltraScale+...
Adam Taylor
Apr 5, 20234 min read
MicroZed Chronicles: Glitch Filtering
Our programmable logic designs are often deployed in applications which can be electrically noisy. This noise can affect the signals that...
Adam Taylor
Mar 29, 20234 min read
MicroZed Chronicles: Getting Started Part Three
Lately we have been discussing helpful tips and tricks, the best development boards and even the best books to reference if you’re...
Adam Taylor
Mar 1, 20234 min read
MicroZed Chronicles: Which Dev Board to Start With?
One of the questions I get asked a lot is which development board is the best for (beginner) FPGA and SOC development. Understandably,...
Adam Taylor
Feb 22, 20234 min read
MicroZed Chronicles: SW Development with Vitis and Visual Studio Code
A lot of my FPGA development takes place within Visual Studio Code where I use it with TerosHDL to create HDL and cocotb for...
Adam Taylor
Feb 17, 20232 min read
MicroZed Chronicles: Hotstate and Programmable State Machines
We often use finite state machines (FSM) when we want to implement control structures in our programmable logic structures. As complexity...
Adam Taylor
Jan 25, 20233 min read
MicroZed Chronicles: Integration and Debugging System
Over the last few weeks, we have been working to create a simple system which allows debugging from a UART into an AXI Lite network. This...
Adam Taylor
Jan 11, 20238 min read
MicroZed Chronicles: From UART to AXI Lite Debug Access
Last week we examined how we could create a UART with AXI Stream interfaces to enable access to AXI buses in device for debugging. In...
Adam Taylor
Jan 6, 20234 min read
Lattice Propel RISC-V, Part Two Software Development.
A few weeks ago, we examined how we could create the hardware element of a RISC-V processor using Lattices Propel tool. The culmination...
Adam Taylor
Dec 30, 20223 min read
Using RPI Pico for System & FPGA Integration
Several times in recent blogs and posts on LinkedIn and Twitter I have mentioned that at Adiuvo we use a lot of RPI Pico’s for hardware...
Adam Taylor
Dec 7, 20226 min read
MicroZed Chronicles: UltraScale+ IO, ODELAY3E and Cascading
We looked recently at the UltraScale+ IO resources which provide a range of capabilities that can be very effective in addressing both...
Adam Taylor
Nov 23, 20223 min read
MicroZed Chronicles: Free Webinars, Workshops, Tutorials and App Notes
One of my passions is sharing information about how we can develop better, more effective FPGA designs. This passion is the driving force...
Adam Taylor
Nov 2, 20222 min read
MicroZed Chronicles: 7 Series DDR3 Debugging
It’s common for many custom FPGA board developments to contain a DDR3 memory. Of course, when we develop a custom board, we need to...
Adam Taylor
Oct 17, 20223 min read
Adiuvo Certus NX Space Development Board
The announcement earlier this year on the collaboration between CAES and Lattice Semiconductor on the availability of space grade...
Adam Taylor
Oct 3, 20223 min read
Nios V/m software development
A few weeks ago, we looked at how we could build the hardware element of our Nios V processor using Quartus Prime and Platform Designer....
Adam Taylor
Sep 21, 20224 min read
MicroZed Chronicles: Cocotb and AXI
A few weeks ago, we looked at the python-based cocotb framework. In that blog, we looked at a simple memory scrubber created around a XPM...
Adam Taylor
Sep 19, 20222 min read
Creating a Nios V/m Hardware Subsystem
In our last blog, we looked at the new Nios V soft-core processor for use in our Intel FPGAs. In this blog, we are going to explore how...
Adam Taylor
Sep 14, 20223 min read
MicroZed Chronicles: Avnet ZUBoard – Temperature Sensor
Ever since the previous overview, I’ve had the Avnet ZUBoard 1CG sitting on my desk. I also just purchased a FLIR C5 thermal imaging...
Adam Taylor
Sep 1, 20223 min read
Using Blue Pearl Visual Verification Suite to Find CDC
A few weeks ago, we talked about how we could synchronise between clock domains in Vivado, I also noticed a couple of questions on r/FPGA...
bottom of page