While writing the HDL is often the easy element of FPGA development, the most challenging and time-consuming element can be verification....

Our programmable logic designs are often deployed in applications which can be electrically noisy. This noise can affect the signals that...

Lately we have been discussing helpful tips and tricks, the best development boards and even the best books to reference if you’re...

Last week we examined how we could create a UART with AXI Stream interfaces to enable access to AXI buses in device for debugging. In...

Introduction As part of our ongoing series of blog posts on high-speed serial transceivers we are going to look at how to create a...

A few weeks ago, we examined how we could create the hardware element of a RISC-V processor using Lattices Propel tool. The culmination...

Several times in recent blogs and posts on LinkedIn and Twitter I have mentioned that at Adiuvo we use a lot of RPI Pico’s for hardware...

Introduction It is a common problem in FPGA design to have to send high-bandwidth data (such as video) between two different FPGAs. ...

Model-based engineering enables engineers to cut down development times by a factor of 5 while maintaining the highest levels of quality.

One of my passions is sharing information about how we can develop better, more effective FPGA designs. This passion is the driving force...

A few months ago, we looked at the AXI Stream FIFO. The AXI Steaming FIFO allows developers to be able to access AXI Streams from AXI...

It is always exciting when new devices are introduced, and this week, AMD Xilinx announced two new devices into the already popular Artix...

It’s common for many custom FPGA board developments to contain a DDR3 memory. Of course, when we develop a custom board, we need to...

On my journey exploring how Cocotb works on a range of interfaces, this week I am going to look at how we can work with AXI Lite and...

A few weeks ago, we looked at how we could build the hardware element of our Nios V processor using Quartus Prime and Platform Designer....

Over the last few weeks, I have been creating a course centered around the Avnet ZUBoard which will be like the MiniZed and Ultra96-V2...

In our last blog, we looked at the new Nios V soft-core processor for use in our Intel FPGAs. In this blog, we are going to explore how...

Verification of both the modules and top-level testing is often more complex and time consuming than creating the HDL. Previously, we’ve...

A few weeks ago, we talked about how we could synchronise between clock domains in Vivado, I also noticed a couple of questions on r/FPGA...

One of the great things about the BRAM in Xilinx FPGAs is its ability to implement error correcting codes (ECC) on the data stored...