MicroZed Chronicles: From UART to AXI Lite Debug Access
Last week we examined how we could create a UART with AXI Stream interfaces to enable access to AXI buses in device for debugging. In...
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Richard Harriss
Jan 9, 20235 min read
High-speed serial transceivers in PolarFire FPGAs
Introduction As part of our ongoing series of blog posts on high-speed serial transceivers we are going to look at how to create a...
Adam Taylor
Jan 6, 20234 min read
Lattice Propel RISC-V, Part Two Software Development.
A few weeks ago, we examined how we could create the hardware element of a RISC-V processor using Lattices Propel tool. The culmination...
Adam Taylor
Dec 30, 20223 min read
Using RPI Pico for System & FPGA Integration
Several times in recent blogs and posts on LinkedIn and Twitter I have mentioned that at Adiuvo we use a lot of RPI Pico’s for hardware...
Richard Harriss
Dec 15, 20229 min read
High-speed transceivers in Xilinx FPGAs
Introduction It is a common problem in FPGA design to have to send high-bandwidth data (such as video) between two different FPGAs. ...
Richard Harriss
Nov 30, 20225 min read
Doing FPGA Cheaper, Better, Faster– Yes You Can Do All Three
Model-based engineering enables engineers to cut down development times by a factor of 5 while maintaining the highest levels of quality.
Adam Taylor
Nov 23, 20223 min read
MicroZed Chronicles: Free Webinars, Workshops, Tutorials and App Notes
One of my passions is sharing information about how we can develop better, more effective FPGA designs. This passion is the driving force...
Adam Taylor
Nov 16, 20223 min read
MicroZed Chronicles: Stream FIFO
A few months ago, we looked at the AXI Stream FIFO. The AXI Steaming FIFO allows developers to be able to access AXI Streams from AXI...
Adam Taylor
Nov 9, 20223 min read
MicroZed Chronicles: New Artix and Zynq UltraScale+ Family Members
It is always exciting when new devices are introduced, and this week, AMD Xilinx announced two new devices into the already popular Artix...
Adam Taylor
Nov 2, 20222 min read
MicroZed Chronicles: 7 Series DDR3 Debugging
It’s common for many custom FPGA board developments to contain a DDR3 memory. Of course, when we develop a custom board, we need to...
Adam Taylor
Oct 5, 20223 min read
MicroZed Chronicles: Cocotb, AXI Streams and AXI-Lite Slaves
On my journey exploring how Cocotb works on a range of interfaces, this week I am going to look at how we can work with AXI Lite and...
Adam Taylor
Oct 3, 20223 min read
Nios V/m software development
A few weeks ago, we looked at how we could build the hardware element of our Nios V processor using Quartus Prime and Platform Designer....
Adam Taylor
Sep 28, 20222 min read
MicroZed Chronicles: MATLAB, Model Composer, and the Avnet ZUBoard
Over the last few weeks, I have been creating a course centered around the Avnet ZUBoard which will be like the MiniZed and Ultra96-V2...
Adam Taylor
Sep 18, 20222 min read
Creating a Nios V/m Hardware Subsystem
In our last blog, we looked at the new Nios V soft-core processor for use in our Intel FPGAs. In this blog, we are going to explore how...
Adam Taylor
Sep 6, 20225 min read
MicroZed Chronicles: Getting Started with Cocotb
Verification of both the modules and top-level testing is often more complex and time consuming than creating the HDL. Previously, we’ve...
Adam Taylor
Aug 31, 20223 min read
Using Blue Pearl Visual Verification Suite to Find CDC
A few weeks ago, we talked about how we could synchronise between clock domains in Vivado, I also noticed a couple of questions on r/FPGA...
Adam Taylor
Aug 31, 20223 min read
MicroZed Chronicles: Memory Scrubbing
One of the great things about the BRAM in Xilinx FPGAs is its ability to implement error correcting codes (ECC) on the data stored...
Adam Taylor
Aug 29, 20222 min read
Rapid Silicon : Raptor Deep Dive
A few weeks ago, we looked at took a high-level view of the open-source tools which are combined to create the Rapid Silicon Raptor tool...
Adam Taylor
Aug 23, 20223 min read
MicroZed Chronicles: 10 Rules for HDL Development.
Writing good, portable, reusable HDL code, that enables the synthesized design to implement at the desired frequency can definitely be a...
Adam Taylor
Aug 10, 20224 min read
MicroZed Chronicles: MATLAB / Simulink HDL Coder
A couple of weeks ago, I mentioned I had invested in MATLAB and HDL Coder to enable generation of RTL code directly from Simulink models....
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