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Adam Taylor
Nov 68 min read
MicroZed Chronicles: Organising Test Benches.
When developing FPGAs there is a critical triad which needs to be achieved for the successful delivery of a project. First we need to...
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Adam Taylor
Oct 94 min read
MicroZed Chronicles: From Bits to Plots: Visualizing XADC Data with Python
One of the things I enjoy is when people reach out with suggestions for blogs and projects that would help them. A recent suggestion was...
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Adam Taylor
Apr 25, 20233 min read
MicroZed Chronicles: Vivado Simulator Code and Functional Coverage
While writing the HDL is often the easy element of FPGA development, the most challenging and time-consuming element can be verification....
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Adam Taylor
Jan 11, 20238 min read
MicroZed Chronicles: From UART to AXI Lite Debug Access
Last week we examined how we could create a UART with AXI Stream interfaces to enable access to AXI buses in device for debugging. In...
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Adam Taylor
Dec 30, 20223 min read
Using RPI Pico for System & FPGA Integration
Several times in recent blogs and posts on LinkedIn and Twitter I have mentioned that at Adiuvo we use a lot of RPI Pico’s for hardware...
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Adam Taylor
Sep 6, 20225 min read
MicroZed Chronicles: Getting Started with Cocotb
Verification of both the modules and top-level testing is often more complex and time consuming than creating the HDL. Previously, we’ve...
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adam@adiuvoengineering.com
Mar 26, 20211 min read
Electronic Engineering Guide - A 57 Page Guide
A simple engineering guide which covers Electronic Design Flow Capacitor and Resistor Selection Grounding Power Distribution Thermal...
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Adam Taylor
Jan 14, 20213 min read
MicroZed Chronicles: GHDL and UVVM Framework
In this post, we will expand the use of GHDL with an open-source verification framework for VHDL called UVVM.
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Adam Taylor
Jan 7, 20213 min read
MicroZed Chronicles: Installing and Working with GHDL for Verification
In this blog let's look at how to install GHDL and use it to simulate our VHDL designs.
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Adam Taylor
Nov 4, 20203 min read
MicroZed Chronicles: AXI Stream Verification IP
The AXI Stream VIP is extremely useful when we want to generate signal and image processing IP that use AXI Stream for interfacing.
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Adam Taylor
Oct 28, 20204 min read
MicroZed Chronicles: Verifying AXI Peripherals
The designs we implement in Vivado often use AXI interfaces. These might be AXI Lite for configuration and control, AXI Memory Mapped
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adam@adiuvoengineering.com
Sep 23, 20204 min read
MicroZed Chronicles: Introduction to RTL Simulation and XSIM
No matter how captured (RTL, HLS, Model Driven), all programmable logic designs should start with agreed requirements that define the...
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