Every digital / FPGA designer should be aware of clock domain crossing between asynchronous clock domains. As our devices get more and...

Last week we examined how we could work with Git and source control on our FPGA designs. Along with working with Git for source control,...

One of the skills which FPGA developers need to master is that of working with source control tools such as git. A few months ago I...

One of the major differences with the Alveo V80 accelerator card is the implementation of the satellite controller. The satellite...

In our first blog and introduction to the new Alveo V80, we examined the features and capabilities of the board itself. In this blog we...

There are many factors that come together to create a successful FPGA design. Not only do we need to have a sensible architecture, IP...

As we look at how to debug our systems, one commonly used approach is to implement an ILA within the design for system observation in the...

As a follow on from last week, one of the techniques I like to use to stimulate or capture data in our FPGA designs is a Linear Feedback...

One of the pivotal architectural enhancements in the Versal family of devices was the introduction of the Network on Chip. Within the...

In our previous blog post, we detailed the successful installation of the XDMA driver and its subsequent testing on the Alveo U55C CMS...

A couple of weeks ago we looked at the Trenz TE0950 development board which contains a Versal AI Edge XCVE2302 device in ES1. This means...

In the 2024 MicroZed Chronicles, we are going to examine Versal in depth with a particular focus on the AI Edge series. We’ve looked at...

One of the biggest challenges you might face if you want to start working with Alveo either on premises or in the cloud is to identify...

Last week we examined the Video Frame Buffer Write (VFBW), which is capable of writing image frames to an external memory. This week, we...