vivado | Adiuvo Engineering

ADIUVO ENGINEERING BLOG

Oct 304 min read

MicroZed Chronicles: Synchronous CDC

Every digital / FPGA designer should be aware of clock domain crossing between asynchronous clock domains. As our devices get more and...

0 comments

MicroZed Chronicles: Automatically Adding Build Version.

Adam Taylor

Jul 95 min read

MicroZed Chronicles: Automatically Adding Build Version.

Last week we examined how we could work with Git and source control on our FPGA designs. Along with working with Git for source control,...

0 comments

MicroZed Chronicles: Working with Vivado and Git

Adam Taylor

Jul 24 min read

MicroZed Chronicles: Working with Vivado and Git

One of the skills which FPGA developers need to master is that of working with source control tools such as git. A few months ago I...

0 comments

MicroZed Chronicles: Alveo Edition, Alveo Versal Example Design, Management Controller.

Adam Taylor

Jun 133 min read

MicroZed Chronicles: Alveo Edition, Alveo Versal Example Design, Management Controller.

One of the major differences with the Alveo V80 accelerator card is the implementation of the satellite controller. The satellite...

0 comments

MicroZed Chronicles: Alveo Versal Example Design

Adam Taylor

May 243 min read

MicroZed Chronicles: Alveo Versal Example Design

In our first blog and introduction to the new Alveo V80, we examined the features and capabilities of the board itself. In this blog we...

0 comments

Adam Taylor

May 214 min read

MicroZed Chronicles: Tackling Timing.

There are many factors that come together to create a successful FPGA design. Not only do we need to have a sensible architecture, IP...

0 comments

MicroZed Chronicles: Using Python to Extract ILA Data

Adam Taylor

Apr 94 min read

MicroZed Chronicles: Using Python to Extract ILA Data

As we look at how to debug our systems, one commonly used approach is to implement an ILA within the design for system observation in the...

0 comments

MicroZed Chronicles: Linear Feedback Shift Register

Adam Taylor

Apr 35 min read

MicroZed Chronicles: Linear Feedback Shift Register

As a follow on from last week, one of the techniques I like to use to stimulate or capture data in our FPGA designs is a Linear Feedback...

1 comment

MicroZed Chronicles: TE0950, DDRMC and NoC

Adam Taylor

Mar 204 min read

MicroZed Chronicles: TE0950, DDRMC and NoC

One of the pivotal architectural enhancements in the Versal family of devices was the introduction of the Network on Chip. Within the...

0 comments

MicroZed Alveo Edition: Understanding Base Address Registers (BARs) for Alveo Application Development

Adam Taylor

Feb 94 min read

MicroZed Alveo Edition: Understanding Base Address Registers (BARs) for Alveo Application Development

In our previous blog post, we detailed the successful installation of the XDMA driver and its subsequent testing on the Alveo U55C CMS...

1 comment

MicroZed Chronicles: Creating a Versal AI Edge Design

Adam Taylor

Jan 174 min read

MicroZed Chronicles: Creating a Versal AI Edge Design

A couple of weeks ago we looked at the Trenz TE0950 development board which contains a Versal AI Edge XCVE2302 device in ES1. This means...

0 comments

MicroZed Chronicles: Versal AI Edge and TE0950

Adam Taylor

Jan 33 min read

MicroZed Chronicles: Versal AI Edge and TE0950

In the 2024 MicroZed Chronicles, we are going to examine Versal in depth with a particular focus on the AI Edge series. We’ve looked at...

0 comments

MicroZed Alveo Edition: Selecting the right Alveo Card

Adam Taylor

Dec 15, 20233 min read

MicroZed Alveo Edition: Selecting the right Alveo Card

One of the biggest challenges you might face if you want to start working with Alveo either on premises or in the cloud is to identify...

0 comments

MicroZed Chronicles: Video Frame Read Buffer

Adam Taylor

Oct 26, 20222 min read

MicroZed Chronicles: Video Frame Read Buffer

Last week we examined the Video Frame Buffer Write (VFBW), which is capable of writing image frames to an external memory. This week, we...

0 comments