The Trenz ZynqBerry Zero is in the same form factor as the Raspberry Pi Zero, but with a Zynq Z-7010. Let's take a closer look.

I need an entry-level scope for a project I am working on so I decided I would pick up a Tektronix TBS1052C and take look at what is inside.

One of the most useful views available in both Vivado HLS and Vitis HLS is the analysis view.

The AXI Stream VIP is extremely useful when we want to generate signal and image processing IP that use AXI Stream for interfacing.

Last year, I examined SLX FPGA and used it to optimize IP Cores for implementation in Vivado looking at security and industrial algorithms.

I recently received the new Trenz TE0802 development board, designed and manufactured by Digilent partner Trenz Electronic.

For complex algorithms, it is often a good idea to first create a model which defines the algorithm’s behavior.

No matter how captured (RTL, HLS, Model Driven), all programmable logic designs should start with agreed requirements that define the...

So, before we look in more detail at Vivado XSIM, let’s first understand the entire verification landscape and what we are trying to achieve

Using Xilinx UltraFast design methodologies can offer significant benefits when implementing designs.

In this blog we explore the Quality of Result Assessment (QoRA) and Quality of Result Suggestions (QoRS).

This blog will break down step-by-step how to download and install the Vitis IDE from Xilinx.