Key Features
AMD Spartan 7 XC7S6 with 6000 logic cells, 5 BRAM, 2 CMT, 10 DSP48
Raspberry PI RP2040 processor providing dual-core Arm M0+ cores running at 133 MHz.
FTDI232H - For JTAG Programming
SDRAM - 64 MBit
4 Pmod - Three for FPGA, one for RPi 2040 -
Ability to fit high speed LVDS transciver on one FPGA Pmod
User Flash - connected to FPGA 32 MBit
QSPIFPGA Configuration PROM 256MBit
Four User LEDs
Four push button switches
Four SPST switches
100 MHz Reference clock
Reference Designs, XDC, Schematics, Vivado board definition can be found here
Application examples inlcude
RPI_FPGA_UART_AXI Vivado 2023.2 Configures a UART in the RP2040 to communicate with the FPGA, sending a protocol over the UART and IP in the FPGA AXI peripherals can be accessed and controlled. In this version three AXI GPIO are connected to three LEDS, the final LED is connected to a AXI timer to demonstrate PWM on the LED. The 4 slide switches are also connected to the AXI GPIO to enable their status to be read over the AXI GPIO. Refer to project here for detials on protocol
SDRAM Vivado 2023.2 - SDRAM example for the SDRAM on the board.
MBV_MCS Vivado & Vitis 2024.1 MicroBlaze V (RISC-V) Microcontroller System implemented on the Spartan 7 see blog
S7_LEO Vivado 2023.2 IO check of all FPGA PMOD IO and 4 LED, walks a LED around all 28 LEDS (4 on board, 24 on Pmod LED - not included) - also connects through the user flash to the RPI for testing
DELTA_SIGMA Vivado 2024.1 Delta Sigma output at 1KHz on PMod 1 pin 1, PWM Sine output at 1 KHz on Pmod 1 pin 2, - external RC needed for recovery
Learn more about the board in these blogs
https://www.adiuvoengineering.com/post/microzed-chronicles-leonidas-board
https://www.adiuvoengineering.com/post/microzed-chronicles-spartan-7-and-axi-over-uart
https://www.adiuvoengineering.com/post/microzed-chronicles-microblaze-v-mcs
https://www.adiuvoengineering.com/post/microzed-chronicles-vivado-board-definitions
