The Agilex FPGAs and SoC FPGAs are high-performance devices which provide developers a range of options across the three variants of devices.
F-Series Devices – The F-Series is intended for the widest range of applications and provides 58 Gbps serdes and high-performance crypto blocks.
I-Series Devices – These are intended for bandwidth-intensive applications and provide support for 116 Gbps, PCIe 5.0, and cache / memory-coherent compute express links.
M-Series Devices – Intended for memory-intensive applications and offers high-bandwidth memory, DDR5 support, and a network on chip for memory interfacing.
These capabilities are implemented using a System in Package (SIP) solution that combines several tiles around the FPGA core to implement the desired variant. The tiles provide a range of capabilities: F-tiles provide a variety of high-performance interfaces like 400 GbE, 116 Gbps, and PCIe controllers; P-tiles and R-tiles provide PCIe; and E-tiles provide Ethernet.
Connections between tiles and the FPGA core use the embedded multi-die interconnect bridge (EMIB).
Depending upon the configuration of the device, the device may include a hard-processor system containing quad-core A53 processors capable of running at up to 1.4 GHz.
I am interested in the Agilex F-Series device because it is fitted to the Agilex transceiver-SOC board I recently received. This board contains the AGFB014R24B2E2EV device which provides 1,400K logic elements, 400K adaptive logic modules, 36 Mbits of eSRAM, 4510 DSP blocks and 24 PAM4 / 32 NRZ transceiver on F-tiles, one PCIe controller on a P-tile, and 12 PAM4/24 NRZ transceivers on E-tiles.
This board provides the developer with the following:
8 GB of DDR4
SODIMM with single-rank DDR4
PCIe Root Complex – Connected to the P-tile transceivers
Quad Small Form-Factor Pluggable 28 – Connected to the E-tile transceivers
Quad Small Form Factor Double Density Interface connected to the E-tile transceivers
Multi-Speed Port (MXP) connected to the E-tile transceivers
This arrangement provides developers with access to 28 Gbps and 56 Gbps lanes available on all QSFP, QSFDD, and MXP connectors.
As you can see, the name transceiver development board aligns very well since most of the accessibility is from the transceivers which are accessible via a range of different interface standards.
To aid with the transceiver application development, several clocks are broken out to SMAs enabling insertion of reference clocks from suitable sources. The board also provides several output clocks for reference or measurement.
Of course, we need to use Quartus Prime in order to create applications for the Agilex device. We can run the board test system when Quartus Prime is installed with the Agilex board. This provides information on the board’s overall reporting system, GPIO status and DDR4 performance, and XCVR testing with the associate loop back plug.
This board looks very interesting and I will be using it to design some projects in and for my first project. I will not be using the transceivers but looking at Nios V the new RISC-V-based Nios processor that is being rolled out and offers support for Agilex devices.
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