One of the many uses of FPGAs is in implementing bespoke communication protocols. At Adiuvo we do a lot of work in the space and high reliability applications, one commonly used protocol which enables ease of communication between nodes is SpaceWire.
At the simplest level the SpaceWire CODEC enables data to be transferred from one node to another.
If you are not familiar with it SpaceWire is uses data strobe encoding similar to IEEE std 1355-1995. Data strobe encoding enables the clock to be recovered by the receiver enabling operation between 2 Mbps and 400Mbps with a default rate of 10 Mbps. This asynchronous nature of the link enables different instruments and equipment’s to operate at an optimal line rate.
In a point to point application, there is no redundancy however, redundancy can be implemented using prime and redundant links between nodes. While networks can be established using a space wire router.
The SpaceWire specification defines the physical level and the data link level of the OSI model. Higher levels of the OSI model can be implemented using protocol like Remote Memory Access Protocol (RMAP) which provides the ability to read and write registers over SpaceWire. Similarly support is also provided for Consultative Committee for Space Data Systems (CCSDS) for telecommand and telemetry.
Of course while SpaceWire is heavily used within satellites, there is also a need for test equipment which can be used for testing individual equipment’s etc during testing of engineering, qualification and flight models.
FPGAs are therefore used in both the satellite equipment and the test equipment. Recently we have developed a SpaceWire CODC and RMAP IO Cores, which are device independent. This allows the cores to be targeted into any FPGA technology.
The Cologne Chip GateMate FPGA is an interesting device which can find applications in the development of test equipment providing protocol conversion to and from space wire. E.g. from Ethernet or USB.
Recently I decided to check the SPW CODEC would function in the GateMate FPGA on the Olimex development board.
The implementation is very simple, the CODEC IP core implemented in the GateMate FPGA is designed to loop back what is received. The CODEC uses AXI Streaming interfaces to transmit and receive information over the SpaceWire interface. When the CODEC establishes a link, a LED is illuminated on the board.
The FPGA design uses a PLL to multiply the 10Mhz clock to a 20MHz clock which is used to clock the CODEC. The CODEC itself is configured to operate at the base line rate of 10 Mbps as I will be testing the IP core using a RP2040 which uses the PIO to implement SpaceWire transmission.
Running the design through the Cologne chip tool flow is very quick, the Pmod is used for the TX and RX data and strobe signals with the allocation being defined in the constraints CCF file.
Implementation wise the CODEC requires, only 421 CPEs, 176 Registers and 1 20K BRAM.
Testing this on the hardware is straight forward with the FPGA programmed with the application and the RP2040 connected via the Pmod we can see the connected LED on both the FPGA board and RPi PICO to show a link is established.
We can then use the RP2040 and a serial terminal on our development machine to send down commands and watch them be echoed back having been received by the FPGA and looped back to the Pico over the SpaceWire links.
This demonstrates we can implement a SpaceWire core within a Cologne Chip FPGA with only 2% of the CPEs and 3% of the BRAM leaving plenty of logic for adding in additional functionality controlled by the SpW CODEC.
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