There are a range of boutique companies developing FPGAs aimed at addressing low to medium-density devices. Cologne Chip is a German company which traces its roots back to 1994 when its predecessor was established to create ISDN ASICs. Nearly 30 years later, Cologne Chip now provides telecommunication ICs, IP and the GateMate FPGA debuting in 2020.
GateMate FPGAs provide between 20,480 (CCGM1A1) and 81,920 (CCGM1A4) Cologne Programmable Elements (CPE).
Each CPE can be configured as either a dual 4-input LUT2 tree, 8-input LUT2, 4-input multiplexor, 1-bit or 2-bit full adder, and 2x2 multiplier. Each CPE also provides developers with two flip flops along with routing.
CPE - Source GateMate Data Sheet
Since there are two flip flops in each CPE, the number of flip flops available is double the number of available CPEs. In addition to the programmable logic provided by the CPEs, the GateMate also provides 40 Kb dual-port SRAM BlockRAMs. These BlockRAMS can be configured as either a single 40 Kb memory or two independent 20 Kb elements. Both configurations support true or simple dual-port configurations. To help developers address their application challenges, the BRAMs provide Error Correcting Code and an integrated FIFO controller.
BRAM - Source GateMate Data Sheet
Of course, these RAMS can be cascaded to create larger memories if required.
Along with CPE and BRAM resources, modern FPGA designs also have complex clocking requirements. To support more complex clocking requirements, GateMate FPGAs provide users with four PLLs in the smallest available device. These PLL are all digital, which can be driven by either a dedicated clock pin or the device fabric. Each PLL outputs the generated clock frequency, in four-phase shifts of 0, 90, 180, 270.
PLL - Source GateMate Data Sheet
When it comes to getting signals on and off chip, the GateMate FPGA offers up to 162 single-ended IO or 81 LVDS IO. When in single-ended mode, the GPIO support LVCMOS 1v2, 1v8 and 2v5. The IO cell is interesting because it provides IO flip flops, programmable delay line and Schmitt trigger inputs.
To help get data on and off board at higher data rates, at least one SERDES pair is provided which is capable of operating at up to 2.5 Gbps. As would be expected, larger devices in the series provide more SERDES.
One of the more interesting features of the GateMate FPGA is that the core voltage can be adjusted to optimize for power or performance. Changing between modes is achieved by changing the core voltage supply from 0.9V (low power) to 1v0 (economy) to 1v1 (speed).
GateMate FPGAs are SRAM-based devices which can be configured using either JTAG or SPI and is fabricated on the global foundries 28 nm super low power process.
I purchased a GateMate FPGA starter kit to take a closer look at the GateMate FPGA. This starter kit provides a CCGM1A1 device which is the smallest of the family and the one I have described in this blog.
The starter kit provides two Pmods, 108 GPIO, 8 LEDs, SMA break out for the SERDES (not populated) and a HyperRAM (S27KS0641).
In the next blog, we will look at the software tool flow for implementing designs on the GateMate and get something implemented on the development board to explore the flow.
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