Over the last few months we have been experimenting with the Colonge Chip GateMAte FPGA on the original development board along with the Olimex GateMateA1-EVB.
A few weeks ago we placed our SpaceWire core on the Olimex GateMateA1-EVB, this was relatively simple design but like all integration activities at times it gets a little interesting and debugging is needed. Historically this is where I would drop in a integrated logic analyser and observe the internal signals and determine what was happening. In this case it was not possible, so we broke out signals and used a logic analyser.
Recently however, I noticed there was a new update from Cologne Chip introducing a Integrated Logic Analyser.
I thought it would be interesting to see how this ILA worked and the ease with which is could be used in a design.
To get started I created a simple design which implemented a Linear Feedback Shift Register (LFSR), clocked at a rate of 1 Hz and then the MSB of the LFSR is fed to a LED output. This provides a random pattern of illumination on the LED!
The first step to get started is to clone the GateMate ILA git repo available here. To ensure we can use the GateMate ILA we need to ensure we have the following installed
Python 3
Python3 packages - numpy, pyftdi, pyvcd,prettytable
GTKWave
With the repo cloned, and the source code written the next stages is to implement the ILA. This is a CLI based approach but once the script is started, the necessary steps are outlined as the script progresses.
I have been running this application from a terminal within VS code and when we run the application we need to ensure the cologne chip board is connected to the board.
To get started, within the gatemate_ila/apps directory issue the following command
python ILAcop.py config -vhd ../../<project directory>/src -t <top entity name>This will configure the ILA for a VHDL top level entity at the project directory provided.
The script will then parse the design and walk us through several stages to configure and run the ILA.
The first stage is the identification of the files in the project.
With the files parsed the next step is to identify the clock we wish to use. For my application I used the external clock input signal.
If we want to change the selected external IO clock we can by typing Y
There will be a list of options presented, in this design we only have one clock.
We then get the option of using an external reset, for this project I deactivated it.
The next stage will list all of the elements found within the design, to be able to observe them we need to select the ones we want to look at. We can do this by filtering.
Selecting Filter, we can then select the module we want to look in to and monitor. I want to monitor the 1Hz counter in the clocking design.
For this example I am going to select the 32 bit counter.
We then get an option to monitor a subset of the vector however, I will be observing it all.
I then finished the instrumentation
The next step is to define the number of samples taken before trigger activation.
The final stage is to define the number of post trigger sample.
We can also if we desire elect to trigger on patterns in the data.
Following confirmation of the advanced triger option the design will implement and build.
Once build it will try to download and execute on the board.
Should we wish to come back to the project and the ILA at a later stage in time we do not need to go through all of this we are able to run the command
python ILAcop.py start 
This will trigger and open GTKWave with the VCD within it, as below we can see the count incrementing.
If we want to change the trigger using the menu presented.
This blog shows how to run through the implementation and creation of the GateMate ILA it is straight forward, while the ILA is a little rudimentary it is a great first step ion the journey of allowing internal debugging.
Workshops and Webinars
If you enjoyed the blog why not take a look at the free webinars, workshops and training courses we have created over the years. Highlights include
Professional PYNQ Learn how to use PYNQ in your developments
Introduction to Vivado learn how to use AMD Vivado
Ultra96, MiniZed & ZU1 three day course looking at HW, SW and PetaLinux
Arty Z7-20 Class looking at HW, SW and PetaLinux
Mastering MicroBlaze learn how to create MicroBlaze solutions
HLS Hero Workshop learn how to create High Level Synthesis based solutions
Perfecting Petalinux learn how to create and work with PetaLinux OS
Embedded System Book
Do you want to know more about designing embedded systems from scratch? Check out our book on creating embedded systems. This book will walk you through all the stages of requirements, architecture, component selection, schematics, layout, and FPGA / software design. We designed and manufactured the board at the heart of the book! The schematics and layout are available in Altium here Learn more about the board (see previous blogs on Bring up, DDR validation, USB, Sensors) and view the schematics here.
Comments