I remember being sat in the crowd at Xilinx Developer Forum 2018 (XDF18) when Xilinx CEO, Victor Peng announced upcoming Alveo PCIe based accelerator cards. This was a radical new direction for Xilinx as they moved up the value chain from supplier of silicon devices to supplier of high performance accelerator cards in a new product line.
Since that date five years ago AMD have acquired Xilinx and Alveo has gone on to become a success story, across both on premises and data centre deployments. With a range of different Alveo cards being developed and introduced to address a diverse range of applications and use cases. To support the target applications each of these Alveo cards have been optimised and provides different logic and memory resources e.g. DDR4, High Bandwidth Memory etc and optimised interfaces e.g. PCIe, CCIx and QSFP etc. This gives developers the ability to select the Alveo card best suited to the application.
If you are not familiar with the Alveo card range they are PCIe based accelerator cards which are designed to integrate with an x86 architecture and provide high performance logic resources which can be used to accelerate bottlenecks in the application.
Applications which benefit from Alveo card acceleration within the data centre include network acceleration, computational storage, video transcoding, electronic trading, data analytics, HPC, and of course AI inference. When it comes to developing these applications both hardware-based flows and software flows are available, leveraging Vivado or Vitis tools, respectively. For software developers, Vitis accelerated libraries can be for example the Machine Learning Suite and Vitis Accelerated Vision libraries. While traditional compute offload applications can be accelerated by leveraging the wider Vitis Accelerated libraries which include features such as data compression, analytics, and HPC. While a typical on premise application might include frame grabbing and image processing from high performance cameras which are connected to the Alveo card using GigE Vision and the QSFP cages.
While each Alveo card is slightly different the architecture of the cards is very similar across the range of cards. They contain a High Performance FPGA, the exact logic resources depend upon the card selected. Configuration memory which holds the configuration of the FPGA depending upon how we develop for the card it will hold either the full application or a shell application which contains a large dynamic region. To monitor the health of the Alveo card there is a satellite controller who acts as the board management controller. We can interact with the BMC as needed in the development.
Of course the critical element of the design is the PCIe interface, this is connected directly between the FPGA and the host machines PCIe controller. When selecting a host system and Alveo card, it is crucial to ensure the best PCIe support possible is achieved. This enables higher bandwidth transfers which results in higher performance of the accelerated application.
External interfaces to the Alveo utilise QSFP interfaces which enable developers to integrate high bandwidth copper and optical connections. These QSFP connections are connected to the
The internal architecture of the FPGA depends upon how we choose to program the card. If we leverage the Vitis flow which is a software based flow and enables developers to leverage the Vitis Accelerated Libraries and the Xilinx Run Time. This is the default development approach the configuration memory on the Alveo card provides a design which provides the user with a static and dynamic environment. The static environment provides the PCIe end point, the card management controller to communicate with the BMC and the clocks and resets. It also provides a dynamic partial reconfiguration region which is used for the application.
Of course if we adopt a Vivado flow to program the application into the Alveo card then we do not start with the static and dynamic regions of the device. We are able to access the full capabilities and interfaces of the device at a low level.
In this blog series we are going to focus on how we can use the Vivado flow, using a Alveo U55C. In our next blog we are going to look at the range of different Alveo cards available along with how to look at selecting the most appropriate. In future blogs we are going to deep dive into how to install the U55C, how to create a base application, working with the interfaces and memories along with how to create a the necessary software applications.
Workshops and Webinars
If you enjoyed the blog why not take a look at the free webinars, workshops and training courses we have created over the years. Highlights include
Professional PYNQ Learn how to use PYNQ in your developments
Introduction to Vivado learn how to use AMD Vivado
Ultra96, MiniZed & ZU1 three day course looking at HW, SW and Petalinux
Arty Z7-20 Class looking at HW, SW and Petalinux
Mastering MicroBlaze learn how to create MicroBlaze solutions
HLS Hero Workshop learn how to create High Level Synthesis based solutions
Perfecting Petalinux learn how to create and work with petalinux OS
Embedded System Book Do you want to know more about designing embedded systems from scratch? Check out our book on creating embedded systems. This book will walk you through all the stages of requirements, architecture, component selection, schematics, layout, and FPGA / software design. We designed and manufactured the board at the heart of the book! The schematics and layout are available in Altium here Learn more about the board (see previous blogs on Bring up, DDR validation, USB, Sensors) and view the schematics here.
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