The goal of professional FPGA development is to deliver projects on quality, on time, and within budget.
Achieving this, however, can be challenging. According to one of the industry’s broadest surveys, Siemens Wilson Group’s 2022 survey, 70% of FPGA projects were behind schedule, with 12% of projects falling over 50% behind schedule.
Using IP (Intellectual Property) components is one approach that can help achieve on-time, high-quality, and cost-effective project delivery.
Compared to when I began developing FPGAs in 2000, we are now in a much better position. Vivado 2024.1, for example, provides 681 IP blocks that we can leverage in our designs. Of course, the applicability of these IP cores depends on the target device family and the device’s capabilities.
Leveraging these IP blocks enables faster development and reduces technical risk by utilizing verified components. Additionally, these IP cores often come with example designs and test benches, which help us understand their operation and usage.
However, not every function we need in our designs is provided in these libraries. In such cases, we may need to develop custom solutions, purchase third-party IP, or use open-source libraries.
We’ve previously explored open-source verification techniques, such as UVVM (Universal VHDL Verification Methodology) and OSVVM (Open Source VHDL Verification Methodology), as well as open-source simulators like GHDL.
In addition, several high-quality open-source libraries provide additional IP cores to support our designs:
Open Logic: This open-source VHDL library offers a variety of IP cores focused on IP peripheral creation. It provides modules for clock domain crossing, memory, FIFOs, arbiters, time division multiplexing, and other features like PRBS, delays, and barrel shifters. For AXI support, Open Logic includes AXI Masters, Slaves, and pipelining. It also offers interface IP for UART, SPI, I2C, among others, making it a valuable resource for AXI endpoints. You can access open logic here.
HDL Modules: This library supplies a range of AXI IP, including interconnects and crossbars, and essential infrastructure like FIFOs. To support simulation, HDL Modules also includes bus functional models and general components, such as ring buffers, LFSR, math functions, and a sine generator. It is well-documented through Read the Docs. You can access HDL Modules here.
SURF (SLAC Ultimate RTL Framework): SURF offers AXI, Ethernet, and device libraries. The device libraries are especially useful, with drivers for peripherals like ADCs and DACs. For verification, SURF employs CocoTB and GHDL, making the process straightforward. You can access SURF here.
PSI Lib: Developed by the Paul Scherrer Institute, this library provides IP modules for memory, FIFOs, clock domain crossing, time division multiplexing, AXI interfaces, and other common modules. You can access the PSI Lib here.
PoC Lib (Pile of Cores): Provided by the Technical University of Dresden, PoC focuses on memory, FIFOs, and I/O controllers. For verification, it leverages CocoTB, OSVVM, UVVM, and VUnit. You can access PoC Lib here.
These are just a few of the libraries available to help you develop solutions without starting from scratch. Many of them integrate well with Vivado, simplifying their use.
One final note: when using these libraries, ensure you read, understand, and comply with their open-source licenses to avoid potential complications.
Workshops and Webinars
If you enjoyed the blog why not take a look at the free webinars, workshops and training courses we have created over the years. Highlights include
Upcoming Webinars Timing, RTL Creation, FPGA Math and Mixed Signal
Professional PYNQ Learn how to use PYNQ in your developments
Introduction to Vivado learn how to use AMD Vivado
Ultra96, MiniZed & ZU1 three day course looking at HW, SW and PetaLinux
Arty Z7-20 Class looking at HW, SW and PetaLinux
Mastering MicroBlaze learn how to create MicroBlaze solutions
HLS Hero Workshop learn how to create High Level Synthesis based solutions
Perfecting Petalinux learn how to create and work with PetaLinux OS
Boards
Get an Adiuvo development board
Adiuvo Spartan 7 / RPi 2040 Embedded System Development Board
Adiuvo Spartan 7 Tile - Low Risk way to add a FPGA to your design.
Embedded System Book
Do you want to know more about designing embedded systems from scratch? Check out our book on creating embedded systems. This book will walk you through all the stages of requirements, architecture, component selection, schematics, layout, and FPGA / software design. We designed and manufactured the board at the heart of the book! The schematics and layout are available in Altium here Learn more about the board (see previous blogs on Bring up, DDR validation, USB, Sensors) and view the schematics here.