In our first blog and introduction to the new Alveo V80, we examined the features and capabilities of the board itself. In this blog we are going to explore the AMD Alveo Versal Example Design (AVED), the AVED provides us a comprehensive starting point for any V80 development.
At a high level the AVED can be broken down into several key elements
Configuration of the Versal CIPS system for the Alveo Versal V80 design e.g. DDR memories, MIO Pinning etc.
Hardware design containing two elements the card management interfaces which manages the SMBus, clocks and resets.
Firmware application which implements the satellite controller running on the Real Time Processing unit with the Versal HBM Design. This firmware is called the AVED Management Control (AMC)
Software application which AVED Management Interface (AMI) which provides host access to control and manage the AMC. This includes a kernel driver, API and Command line tool.
The AVED is recreated by using a build flow script and it is recommended this script is the starting point for all developments targeting the Alveo V80.
In this blog we will examine the recreation of the AVED for deployment on the Alveo V80. To do this I will be using Vivado 2023.2.1 which is the base Vivado 2023.2 installation with update one applied.
The AVED design is available on the AMD GitHub here this repository contains nearly everything required to recreate the AVED on the Alveo V80. This includes the HW design in Vivado, the FW using Vitis and SW for deployment on the host.
Note, to build this design you will need to SMBus IP and license provided via the Alveo V80 lounge.
To recreate the design we can use the build_all script which is available under the HW directory of the repository.
This will take a several tens of minutes to complete but once completed the PDI image will be available for use with the Alveo V80. With this PDI we are then able to update the design elements stored within the OSPI flash. The OSPI Flash uses a Fash Partition Table, to enable Vivado hardware Manager to be able to program the OSPI flash the AVED build flow prepends a FPT Binary image to the PDI to enable this.
Should we desire we can open the hardware design in Vivado and explore the configuration implemented in the AVED.
Expanding the hierarchical blocks will show the details of the IP blocks below which implement the SMBus interface and management of the clocks and resets.
This AVED provides us the base example from which we are able to start our developments which leverage the QSFP56 and MCIO ports available on the V80. The total logic footprint of the design is less than 0.25% utilisation.
With the build completed we have all of the elements we need to configure the V80 and ensure the card functions correctly in our system. We can leverage the AMI and AMC software to report on status of the card.
To get started with transferring between the Host system and the V80 we need to leverage the AMD QDMA host drivers. We will look at the software side of the AVED and the installation of the QDMA drivers in the next blog.
Workshops and Webinars
If you enjoyed the blog why not take a look at the free webinars, workshops and training courses we have created over the years. Highlights include
Professional PYNQ Learn how to use PYNQ in your developments
Introduction to Vivado learn how to use AMD Vivado
Ultra96, MiniZed & ZU1 three day course looking at HW, SW and PetaLinux
Arty Z7-20 Class looking at HW, SW and PetaLinux
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HLS Hero Workshop learn how to create High Level Synthesis based solutions
Perfecting Petalinux learn how to create and work with PetaLinux OS
Embedded System Book
Do you want to know more about designing embedded systems from scratch? Check out our book on creating embedded systems. This book will walk you through all the stages of requirements, architecture, component selection, schematics, layout, and FPGA / software design. We designed and manufactured the board at the heart of the book! The schematics and layout are available in Altium here Learn more about the board (see previous blogs on Bring up, DDR validation, USB, Sensors) and view the schematics here.
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