One of the main challenges FPGA designers face, especially those new to FPGA design is how to achieve timing closure. While it seems challenging this does not necessarily have to be the case, lets take a look at how we can use Vivado to make a baseline timing closure.
A baseline timing closure is designed to achieve timing closure with the simplest set of timing constraints possible. Instead of waiting until the end of the bit stream generation to determine if the design closes timing we will be using a incremental approach which examines the designs timing performance at the synthesis, optimisation, place and route stages.
To start working towards a baseline timing closure we will first synthesise the design, following completion we will work through the following stages.
Post Synthesis - Use Timing Wizard to define constraints (if not already defined) skip the IO constraints. Check for methodology violations by reporting the methodology, should any methodology violations be identified we need to correct these.
Optimize Design – Run the design optimisation and report timing. Examine the timing report and resolve any timing paths which report a negative slack (WNS). Again report on the methodology and correct any violations.
Place Design – Place the design and report timing. As with the optimize design stage examine the timing report and resolve any timing paths which report a negative slack (WNS). Also resolve any hold issues which are greater than -0.5 ns.
Route Design – Route the design and report timing. Resolve any remaining timing violations, run DRC and methodology reports to validate the approach.
This incremental approach assists us in achieving timing closure, I would not expect the process to be linear, but iterative as issues are raised and addressed.
The timing report will provide us guidance which we can use to help address the issues in the design.
High Cell Delay - To address a high cell delay, we can take several approaches. Modify the RTL to use parallel or more efficient operator. Insert into the logic cone pipeline registers (see perfecting pipelining) and enable synthesis retiming. Ensure BRAMs, URAM and DSP are correctly pipelined, ensure resets (see working with resets) are correctly defined for registers to be correctly packed into primitives such as DSP48. Optimise SRL paths and enable optimisation by ensuring constraints such as KEEP.DONT_TOUCH and MARK_DEBUG are removed.
High Route Delay – To address a routing delays, we need to review the constraints and floor plan. Examine any high fan out nets and optimise or enable replication, we should also consider control set optimisation which might lead to congestion. Control set optimisation enables us to move set / reset and clock enables to be implemented in the data path or directly connected to the flip flop pin. One of the things we might also do for timing closure inter module is to leverage a placement wrapper around the module. This placement wrappers registers all of the IO, as such it provides the placement too the flexibility to locate the registers on the routing between the modules.
High Clock Skew / Uncertainty - To address clock skew, parallel buffers can be considered in case of cascaded buffers, ensure timing constraints are correctly defined, especially between asynchronous clocks. We can also leverage the clock_delay_group constraint. If clock uncertainly is the issue we could examine optimising the MMCM settings or using a BUFGCE_DIV (detailed example here and here) in its place
Of course to ensure we achieve timing closure this also starts with generating RTL which provides the synthesis, and implementation stages in Vivado the most flexibility. We recently ran a webinar which examined how to design for Vivado here.
As timing is such a key area on the 31st October 2024 we will be running a webinar on timing closure and walking through a real world example of how we are able to achieve a baseline timing closure. If you want to come along you can register here and if it is not at a convenient time it will be available shortly after on our YouTube channel.
Workshops and Webinars
If you enjoyed the blog why not take a look at the free webinars, workshops and training courses we have created over the years. Highlights include
Upcoming Webinars Timing, RTL Creation, FPGA Math and Mixed Signal
Professional PYNQ Learn how to use PYNQ in your developments
Introduction to Vivado learn how to use AMD Vivado
Ultra96, MiniZed & ZU1 three day course looking at HW, SW and PetaLinux
Arty Z7-20 Class looking at HW, SW and PetaLinux
Mastering MicroBlaze learn how to create MicroBlaze solutions
HLS Hero Workshop learn how to create High Level Synthesis based solutions
Perfecting Petalinux learn how to create and work with PetaLinux OS
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