The ability to get data on and off chip, at high bandwidth is critical, we are fortunate that our FPGA provide a range of high performance IO which can support. Of course the highest performance IO bandwidths are provided by the Gigabit Transceivers which provide data rates from X to X Gbps per link.
In our devices these GTs are grouped in quads which provide four transceivers, along with this are two reference clocks. These reference clocks can be used by ether the QPLL (LC Tank based) or CPLL (Ring Oscillator based).
For each quad there are two reference clocks (0 and 1), these reference clocks can be used to not only to clock the quad they are directly connected but also up to two quads above and below.
This means for a single Quad the clocking looks as below
For multiple quads, this scales as would be expected.
The reference clock can be configured as either an input, when the reference clock is provided to the pins, or alternatively as an output when the reference clock pins, output the clock. In this blog we will be looking at the input configuration, though I will come back and look at the output configuration in another blog soon.
The architecture of the reference clock can be seen within the IBUFDS_GTE3/4, this structure includes the logic termination. Along with an output to the channels or common block contained within the quad. There is also an output which is able to connect to the clocking structures within the FPGA.
This output can also be used to divide the clock output by two if desired.
We are able to implement the IBUFDG_GTE within our logic designs simply we can do this using two macros which are defined within UG974 UltraScale Architecture Libraries guide.
The first macro we need to instantiate id the IBUFDSGTE, if we are instantiating this within a IP Integrator design as I am for this example, the macro can be instantiated from the utility buffer IP within the library.
If you are doing a pure RTL approach, you are able to see a template from the language templates within Vivado.
With the IBUFDS_GTE implemented within the design the next step is to instantiate the BUFG_GT which connects to the clock network. Again if we are developing using an IP integrator flow, we are able to instantiate this by using a utility buffer IP. Alternatively if an RTL approach is to be used we can again leverage the language templates.
The completed IP Integrator design, demonstrates how these blocks should be connected together to achieve a working solution.
To test this design I created a simple test bench which pulled in the block design which would be implemented in the design and used a simulation clock generator to provide stimulus.
Running this in Vivado simulator showed the IBUFDSGTE and IBUFG_GT were functioning correctly as expected.
Of course the proof of the pudding is achieving a successful implementation targeting a device. For this reason the project was configured to target a ZCU106 board. This uses a configurable clock generator to provide a 156.25 MHz clock into quad 224, for a simple demonstration I will use this as the input reference clock and output the resultant clock on a HPC pin.
The reference clock is connected to pins AA9 and AA10, while the output clock is connected to A11 on bank 68 which routes to the FMC connector.
Of course the proof of the pudding is achieving a successful implementation targeting a device. For this reason the project was configured to target a ZCU106 board. This uses a configurable clock generator to provide a 156.25 MHz clock into quad 224, for a simple demonstration I will use this as the input reference clock and output the resultant clock on a HPC pin.
The reference clock is connected to pins AA9 and AA10, while the output clock is connected to A11 on bank 68 which routes to the FMC connector.
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