Regular readers of this blog will know I am big fan of working with higher levels of abstract to develop our programmable logic designs. They will also know that I am also a champion of model based design, using Matlab and Simulink.
One of the easiest ways to leverage model based design with working with AMD devices is Vitis Model Composer. If you are not familiar with model composer it is a model-based design tool that works with Simulink. Using model composer we can accelerate development of signal and image processing. This is important as for many large devices such as Versal it is only by using model based design we are able to truly leverage its capabilities.
Versal provides developers with the not only the programmable logic but also the AI Engines. While optimised for AI implementation the AI Engine Tiles also provide support for many DSP features as well such as Filters and Beam Forming. Thanks to the DSP Vector extensions also provided in the vector processor.
To help learn how to access the DSP Vector extensions using Model Composer AMD have a range of tutorials available on the model composer github. Examples of these include 2DFFT, Filtering in the Frequency Domain and Single Stream Super Sample Rate FIR.
As I am always keen to explore I thought it would be interesting to look at one of these demos and implement it to run on a VCK190.
The first step in the process was to clone the repo and open the selected design example, for this exercise I chose the 2D FFT.
With the design open we can see there are two element the Versal design and the Simulink reference.
We can explore the design and its configuration for example clicking on the AIE block will open the contents of the AIE. This presents us with two FFT which are configured to be implemented in the AIE.
To understand a little more about how the AIE can be used for FFT etc, you can explore the library browser which under the AMD Toolbox will list a number of functions which can be implemented in the AIE.
Back at the top level of the design we can simulate the design and see the results of the image. The nice thing about simulating and working at this high level is that is makes it easy to work with standard data formats and as we are not simulating clock cycles the simulation completes quickly.
Once we are happy with the simulation, we need to think about deployment onto to the hardware in this case a VCK190. Again there are a number of tutorials which are provided on the git hub which will walk you through deploying the Vitis model composer design to hardware.
Clicking on the model composer hub block we can set the target for the VCK190 and generate the code required for the AI Engines. The Vitis Model Composer Hub, is the key element in working with Vitis Model Composer using the Hub we are able to control a wide range of configurations from the target hardware (device or board) to range of options on the code generation. The VMC Hub is intelligent and the options provide change depending on the flow being used AIE, HLS, or HDL. As we are targeting the AIE for this application our settings enable us to configure the compiler and simulator options.
We can also configure if we wish the VMC Hub to generate a test bench from the test vectors when creates the code. This is very important as it allows the developer to be able to visualise the performance of the design in the AIE. To aid us in understanding the performance of the code we are able to use the AIE simulation output and throughput along with performing in depth analysis using Vitis Analyzer.
The hardware options for the VMC Hub are more focused enabling us to generate either a library or hardware validation code. This generated hardware is able to target either baremetal or petalinux OS running on the target hardware.
Both settings for simulation and hardware generation are straight forward and allow us to simply and easily change our desired configuration. From example from validation to deployment at the click of a button.
It is using the Hub we are able to configure our project to run both the simulation initially and then generate the hardware. For the project we are examining at the moment we are going to set the following options.
Creating a Test Bench
Running Cycle-approximate AIE Simulation after generation
Plot AIE Simulation output and estimate throughput.
Once the code is created we are able to examine the source generated as shown below
Really nicely the test bench created compares the results of the generated code against the Simulink simulation. The result will be either Match, Partial Match or Do Nor Match, Match and Partial match are considered passes, the difference between the two is, a partial match has extra samples in either the Simulink of AI Engine simulator test bench not accounted for in the others. This is due differences in stop time between the two different simulators.
Of course, now we want to run the application on the target board and verify its performance. In the Vitis Model Composer Hub we on the code generation tab we are able to select bare-metal or PetaLinux solution. For this example we will generate the bare-metal target. We will also request the generation of a boot.bin file which boots the VCK190.
Booting the VCK190 and observing results on a terminal will show the tests being performed and successful completion.
Workshops and Webinars
If you enjoyed the blog why not take a look at the free webinars, workshops and training courses we have created over the years. Highlights include
Professional PYNQ Learn how to use PYNQ in your developments
Introduction to Vivado learn how to use AMD Vivado
Ultra96, MiniZed & ZU1 three day course looking at HW, SW and Petalinux
Arty Z7-20 Class looking at HW, SW and Petalinux
Mastering MicroBlaze learn how to create MicroBlaze solutions
HLS Hero Workshop learn how to create High Level Synthesis based solutions
Perfecting Petalinux learn how to create and work with PetaLinux OS
Embedded System Book
Do you want to know more about designing embedded systems from scratch? Check out our book on creating embedded systems. This book will walk you through all the stages of requirements, architecture, component selection, schematics, layout, and FPGA / software design. We designed and manufactured the board at the heart of the book! The schematics and layout are available in Altium here Learn more about the board (see previous blogs on Bring up, DDR validation, USB, Sensors) and view the schematics here.
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