MicroZed Chronicles: Open Source VHDL Verification Methodology (OSVVM)

Over the years, we have looked at many different verification frameworks like cocotb and varying approaches when working with AMD AXI Verification IP (VIP), for example. This last week, I attended the European Space Agency’s Space FPGA User Conference and bumped into Jim Lewis, the creator of OSVVM or Open Source VHDL Verification Methodology.

OSVVM is a VHDL-based verification methodology which provides developers with the following:

• VHDL verification framework

• Verification utility library

• Scripting API

• Co-simulation ability

These features enable OSVVM to provide a structured transaction-based verification framework. To accelerate development, OSVVM provides API transactions for commonly used memory mapped and streaming interfaces such as AXI, AXI Lite, and UART etc.

Built on top of the transaction layer is the ability to perform constrained random testing, functional coverage and implement score boards and error logging. OSVVM works with a range of commercial and open-source simulators including GHDL and ModelSim.

Installing OSVVM is very simple and includes cloning the git repo, opening our simulator of choice and building the libraries and demo examples.

The structure of an OSVVM test bench is a very interesting and uses a combination of VHDL files and scripts.

At the center of OSVVM is the Unit Under Test (UUT). Each of the UUT interfaces is connected to an OSVVM verification component from the component library within a test bench harness. Clocks and resets are provided by the test bench utility package. Also contained within this test harness is a test control component. It is this component which sequences the tests to be applied to the UUT.

The test controller then has at least one architecture which binds to its entity and applies the transactions to the UUT.

The application of the transactions is controlled by OSVVM scripts with two scripts typically used. The first script is used to define the structure of the test harness and the files included in it. The second script is used to apply the test sequences. Using a record interface, the test controller connects to the verification components such as UART etc.

Let’s take a look at this with a simple UART example. We will create the following files for this example:

1. UART RTL – The UUT of the design.

2. UART test harness – contains the UUT and the verification components.

3. Test controller – connects to the UART verification components in the test harness over using the records.

4. UART test – The tests to be applied to the UUT.

5. Script files to run the verification.

This approach is like the reference example except I inserted an AXIS UART. The reference design runs the UART verification Tx and Rx back-to-back. This enabled me to understand the flow in more detail because creating a basic example myself always helps me understand the flow better. Of course, we need to add in the UART RTL files into the correct script.

Once these files were complete, I opened ModelSim and changed directory to the location of the files.

To enable OSVVM, I ran the startup script and then proceeded to build test bench script which compiles all the HDL files and libraries and loads the design.

One very nice feature of OSVVM is that it creates an HTML summary report at the end of the simulation along with a transcript etc. from the simulation.

Frameworks like OSVVM helps us focus on performing verification and not having to write the test infrastructure from scratch.

Verification is one of the most important aspects of FPGA design and we will come back and look at concepts like functional coverage and constrained random testing in another blog soon.

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