Designers are well aware of the acronym SWaP-C, which relates to the Size, Weight, Power and Cost. FPGAs can be very useful in assisting developers to achieve the desired SWaP-C, one of the more difficult aspect for many applications faced with SWaP-C challenges is the achieving the desired power.
Regular readers of this blog will know that I am a great believer in the system approach to engineering. As such when we are faced with addressing power constraints, we need to accurately set a power budget. The power budget defines the allocation of power to a sub system from the overall available input power.
Doing an accurate power budget can be the difference between a successful project and one which has several issues as the integration proceeds and the power taken by sub systems is outside their power allocation.
This normally results from inaccurate power estimation during the initial power budgeting phase. Achieving an accurate power budget can be a challenge as it needs the an accurate early prediction which is then firmed up and refined as the project progresses.
When we are working with FPGA, we refine our power estimation in a multi stage process using first the power estimation spreadsheet. Followed by refining the power estimation using Vivado power estimation facilities. There is a great application note on determining an accurate worst-case power analysis here.
I was talking to someone about this in the week and it struck me the Embedded System Tile we created could be used in a interesting way to determine the accuracy of the power estimation tool against the actual device. The tile has minimal supporting circuit for the Spartan 7 FPGA as such the main element of the power dissipation on the board is the actual FPGA.
Starting with the excel power estimation spreadsheet, we are able to define the clocks, LUTs, FF, BRAMS, DSP, IO along with their clock and toggle rates. Crucially in this spreadsheet we can also define the process type (select maximum to ensure worse case), the airflow, board size, and implementation optimisation (select default).
We can estimate the resource requirement from IP product guides, these provide excellent details on resource requirements for different devices and configurations.
Selecting the IP blocks, to implement a MicroBlaze V microcontroller with JTAG Debug, GPIO, AXI IIC and UART operating at 100MHz. With the settings at maximum and default optimisation provides a predicted power dissipation of 0.328 W.
Using the worse case number if important as the design needs to be able to accommodate variations in the PVT.
What I would expect to see when using Vivado’s power estimation abilities is a slightly lower power dissipation as the resource optimisation is more accurately know, also is the switching activity.
The complete design is as shown below
The power estimation results for the implemented design in Vivado show a high confidence as I associated the MicroBlaze elf file with the design and ran the simulation.
When the simulation was run I captured a switching activity interchange file (SAIF)
Running the simulation you can see the processor begin to execute and transmit the initial welcome message over the UART.
Using this information and providing it to the Power Estimation tool within Vivado produces a predicted power of 0.305W on chip.
Building the design and programming the configuration memory, enabled me to monitor the current and power drawn by the Embedded System Tile using a joule scope.
This showed the entire Tile takes 102 mA on average from the 5V supply.
To determine the power taken by the FPGA we need to first determine the power efficiency of the convertor. The RT7273GQW to generate the three rails required, at low load currents has an efficiency of 70%.
This means the 0.52 W drawn from the power supply equates to a load power of 0.36 W. We also need to determine the current drawn by the few additional components on the board. These are the Oscillator, Boot Memory and Serial RAM. There is also an done LED which is illuminated and will account for a reasonable element of the power budget.
Calculating the power dissipated by the LED, Oscillator, Boot Memory and Serial RAM accounts for 93.9 mW
Current (A) | Power (W) | |
LED | 0.0058 | 0.0191 |
Oscillator | 0.0145 | 0.0479 |
Boot Mem | 0.0001 | 0.0005 |
RAM | 0.0080 | 0.0264 |
0.0939 |
The FTDI USB JTAG interface on the board is powered from the USB connection and is not accounted for in the calculations as such.
This means the FPGA power being taken is 0.36W minus 0.0939W or 0.2695W which when compared to the Vivado prediction of 0.287W is within 6% of predicted value.
Having done this I want to do further work on this and I think with a board which has a INA226 monitor in line with the power supplies such that we can investigate the accuracy further.
But for now it is good that when predicting the power for a relatively low power design we are able to get within 10% of the actual dissipation.
Workshops and Webinars
If you enjoyed the blog why not take a look at the free webinars, workshops and training courses we have created over the years. Highlights include
Upcoming Webinars Timing, RTL Creation, FPGA Math and Mixed Signal
Professional PYNQ Learn how to use PYNQ in your developments
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Arty Z7-20 Class looking at HW, SW and PetaLinux
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HLS Hero Workshop learn how to create High Level Synthesis based solutions
Perfecting Petalinux learn how to create and work with PetaLinux OS
Boards
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Adiuvo Spartan 7 / RPi 2040 Embedded System Development Board
Adiuvo Spartan 7 Tile - Low Risk way to add a FPGA to your design.
Embedded System Book
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