top of page

MicroZed Chronicles: Rounding

Writer: Adam TaylorAdam Taylor

Programmable logic is great for implementing mathematical algorithms for a range of applications from filtering to machine learning. Recently we have examined how mathematical operations are implemented within programmable logic using fixed point implementations. Including a detailed Hackster project.



One of the lessons we have learned as we worked with fixed point numbers is very quickly we can experience significant bit grown when adding or multiplying numbers together.

 

It is natural in our application that we may want to reduce the number of bits especially in the fractional bits.

 

However, how we do this may have an impact on our algorithms performance and output. For example if we may introduce offsets or biases within the result.

 

So in this blog we are going to take a look at how different rounding schemes work when we are working with fixed point maths in FPGAs. Lets look at the different rounding methods we can use in our FPGAs and when we might use them or not. Most of these can be very easily implemented within programmable logic using the VHDL 2008 fixed package types.

 

Truncation – The simplest approach which just truncates the bit vector, as such it requires no additional logic to implement. It does however introduce a bias towards zero which is not useful for many applications. This is also often called rounding towards zero or fixed rounding.

Algorithm  = Truncate fractional LSBs

Towards +Inf – This approach rounds the number towards positive infinity, it ensure a number will never decrease when it is rounded. For example 1.375 would round to 2, while -1.375 would round towards -1 this is rounding style is often referred to as taking the ceiling. It does however introduce a upwards bias as the result is never allowed to decrease.

Algorithm = IF fractional !=0 
		integer = integer  + 1; 
		fractional = 0 
	     ELSE
		fractional = 0

Towards -Inf – Similar to rounding towards positive infinity, rounding towards negative infinity ensure the value never increases. As such it adds in a downwards bias as the result is never allowed to increase. An example of this is 1.375 would round to 1 while -1.375 rounds to -2. This rounding method is often called talking the floor.

Algorithm = IF fractional !=0 
		integer = integer  - 1; 
		fractional = 0 
	     ELSE
		fractional = 0

Round Half Up – This rounds to the nearest integer if the fractional part is equal to or greater than 0.5, otherwise it rounds down. Rounding in this style adds in a upward bias.

Algorithm = IF fractional >= 0.5 
		integer = integer  + 1; 
		fractional = 0
	     ELSE
		fractional = 0

Round Half Down – This rounds down if the fractional part is greater than 0.5, otherwise it rounds down. Rounding in this style adds in a downwards bias.

Algorithm = IF fractional > 0.5 
		integer = integer  + 1; 
		fractional = 0 
	     ELSE
		fractional = 0

Convergent Rounding – Unlike all of the other rounding schemes presented convergent rounding is a unbiased rounding scheme. Convergent rounding does this by rounding to the nearest even integer when the value is half way between two integers. For fractions greater or less than 0.5 it rounds up, other wise it rounds down. This adds a little extra complexity however, it produces a result which is unbiased, as such it is popular in DSP and ML/AL applications.

Algorithm = IF fractional > 0.5 
		integer = integer  + 1; 
		fractional = 0 
	     ELSE IF fractional  = 0.5 
	     	ELSE IF odd(integer) 
			Integer = integer +1
			fractional = 0
	  	ELSE 
 			Integer = integer 
			fractional = 0
	  	ELSE
			Integer = integer 
			fractional = 0

Implementing these functionalities within a VHDL or Verilog function which should enable reuse of these rounding schemes across several applications as we need them.

 

In the mean time the table below summarizes the options above to provide a good reference of the different rounding styles, the logic impact and of course any bias.

Scheme

Bias

Best For

Complexity

Truncate

Zero bias

Fast computations

Very low

+∞ (Ceil)

Upward

Conservative limits

Low

-∞ (Floor)

Downward

Safety-critical applications

Low

Round Half Up

Upward

General computing

Low

Round Half Down

Downward

General computing

Low

Convergent

Unbiased

DSP, AI

Moderate

UK FPGA Conference


FPGA Horizons - October 7th 2025 - THE FPGA Conference, find out more here


Workshops and Webinars


If you enjoyed the blog why not take a look at the free webinars, workshops and training courses we have created over the years. Highlights include



Boards


Get an Adiuvo development board



Embedded System Book   


Do you want to know more about designing embedded systems from scratch? Check out our book on creating embedded systems. This book will walk you through all the stages of requirements, architecture, component selection, schematics, layout, and FPGA / software design. We designed and manufactured the board at the heart of the book! The schematics and layout are available in Altium here   Learn more about the board (see previous blogs on Bring up, DDR validation, USB, Sensors) and view the schematics here.

bottom of page