One of the great things about FPGAs is not only the configurable logic blocks, BRAMs, DSPs and a host of other useful peripherals but also the incredible flexibility of the IO structures.
These IO structures enable us to develop a complex interfacing solutions from Gigabit transceivers with the GTs which provide a range of bit rates from the 6 Gbps to 112Gbps depending on the device selected. To IO structures which support a range of signal ended and differential standards from LVCMOS to LVDS and DDR5 Phys, MIPI DPHys and beyond.
It is however not just the IO standard support it is the additional capabilities provided by these IO structures which make them truly useful from Double Data Rate flip flops to fine precision IO delays, Serial / Parallel Conversion and Digitally Controlled Impedance. These Io structures are what enable the near any to any interfacing provided by FPGAs.
The type of IO structures available for use depend upon the device selected, if we select a Versal device we are provided HDIO for High definition interfacing e.g. 1.2 to 3.3 V and XPIO for high performance interfacing at 1.2V and below. When working with UltraScale or UltraScale+ devices are provided High Definition IO and High Performance IO, HD I/O provides compatibility with slower interfaces operating at up to 3.3V while HP I/O provides high speed interfacing capabilities. The upcoming Spartan US+ will provide developers with XP5IO from the Versal range which enables support for DDR5 Interfacing. Finally the 7 series provides users with High Performance and High Range IO.
Depending on the family and IO type you are using the capabilities provided by the IO structure may vary. For example 7 series HR IO provide an IDELAY but only HP IO have both IDELAY and ODELAY.
Within the 7 series HD and HP I/O we have the following IO Structures.
When it comes to working with the available IO structures we have the option of instantiating and configuring the specific components required directly e.g. IDELAY etc. This is something we have examined before in the 7 series when we looked at working with the IDELAY and ODELAY.
However, if we desire to use a combination of these IO capabilities we can use the Select IO Wizard to configure the IO structures as necessary.
Typical applications of these IO structures is implementing serialisation / deserialization or alignment of data such as Camera Link Tx, Rx, DVI Tx, Rx or chip to chip communication.
Using this wizard we are able to define the bus direction, data rate (SDR, DDR), serialisation factor (2 to 8 SDR, or 4 to 14 DDR) and IO standard.
We can also control the clocking set up internal or external and define the clock and data delays. When it comes to clocking the IP created by the Wizard we need to provide two clocks, the first is the clock and the second the divided clock. The relationship between the two is key the clock input should be N times the divided clock e.g. for a serialisation rate of 7 it should be seven times the frequency of the divided clock for example.
If we desire we can also also use one of the predefined templates.
Lets take a look at creating a simple Camera Link Tx / Rx pair. Camera Link while an old technology it can be useful for some industrial and scientific systems. It also allows us to demonstrate this wizard effectively.
For this example we will use a counter to mimic the pixel data and the completed design looks as below. I have configured the clk in to 70MHz and the clk div to be 10 MHz. One the receiving end of the camera link module we enable the bit slip generation.
I also wrote a simple module to ensure the IO is reset properly being released after the clock reset.
There appears to be an issue with the camera link clock output being incorrect hence I used the internal clocking option on the receiver.
If the system is working correctly we should be able to see the count be decoded correctly on the camera link receiver output in simulation, if we use the bit slip enable inputs to align the output against the expected clock.
This is a simple introduction to the Select IO wizard, my plan is to look at this in all different families of the device. I am also going to look at the chip to chip interfacing as that could be interesting for a number of projects.
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