Over the last few months we have been developing a tile, which contains a Spartan 7 XC7S25 and all of the supporting peripherals necessary to implement a FPGA based solution.
One of the reasons we developed these boards was to enable a simple, and risk free solution to implementing FPGAs for a range of solutions. One common application for smaller FPGAs is in providing system control for a larger FPGA such as a UltraScale+ or Versal device.
In this role the system controller is responsible for controlling the environment of the larger FPGA, as such the system controller will
Control power supply sequencing.
Monitor power supplies and current rails to ensure the are within expected tolerances.
Adjust power supply output voltages for adjustable IO voltages such as FMC, and IO Banks.
Configure adjustable clocking networks for the desired output frequencies
Report status information on the boards configuration e.g. Voltage settings, clocking settings and configuration settings along with information such as board IDs and MAC addresses etc.
Many of these require traditional embedded system communication interfaces, for example many adjustable voltage and clocking devices use I2C or a derivation such as SM Bus.
The GPIO of the system controller can be useful also for the setting of discrete options on the board.
In this blog we ae going to look at the creation of a system which uses a MicroBlaze V, combined with a I2C, and UART to implement an example system controller.
The system controller will use the I2C to connect to the Sysmon of a UltraScale+ device ona ZCU106. The Sysmon connections are made available externally, in that design.
The MicroBlaze V running on the tile will run a simple command line interpreter (CLI) the running of the CLI enable a controller application on a remote PC to be able to create a GUI and interface easily with the system controller.
This CLI will therefore be able to send commands over the IIC to communicate with what is attached to it. If we have several different elements we could add a second AXIIC, SPI or anything which is needed.
To demonstrate this project I reused the ZCU106 application I created for the blog on I2C and Sysmon access, this makes breaks out the I2C access easily.
First thing is first I created a Spartan 7 Tile board definition which could be used by Vivado to define the FPGA on the Spartan 7 Tile and its interfaces.
The hardware design for the Spartan 7 Tile, contains the following elements
MicroBlaze V – Configured as a Microcontroller pre-set with 64KB of memory.
AXIIC – Configured for 100Khz Operation
AXI UART Lite – Configured for 9600 baud
AXI GPIO – Connected to the two user LEDs
AXI Interrupt controller – Connected to the AXI UART Lite and AXIIIC modules interrupt outputs.
MDM – MicroBlaze Debug Module
Clocking Wizard – Configured to provide a 100MHz clock – we have 100 MHz on the board but this provides flexibility for changing performance if desired.
The completed diagram can be seen below
The next stage is to assign the IO from the tile to the connect to the UART cable and ZCU106 over flying leads.
Using the schematics, I assigned pins from bank 14 which are powered from 3v3 on board.
set_property IOSTANDARD LVCMOS33 [get_ports clk_in1_0]
set_property PACKAGE_PIN M9 [get_ports clk_in1_0]
set_property IOSTANDARD LVCMOS33 [get_ports IIC_0_scl_io]
set_property IOSTANDARD LVCMOS33 [get_ports IIC_0_sda_io]
set_property PULLTYPE PULLUP [get_ports IIC_0_scl_io]
set_property PULLTYPE PULLUP [get_ports IIC_0_sda_io]
set_property IOSTANDARD LVCMOS33 [get_ports UART_0_rxd]
set_property IOSTANDARD LVCMOS33 [get_ports UART_0_txd]
set_property PACKAGE_PIN N15 [get_ports UART_0_rxd]
set_property PACKAGE_PIN P14 [get_ports UART_0_txd]
set_property PACKAGE_PIN P15 [get_ports IIC_0_scl_io]
set_property PACKAGE_PIN R13 [get_ports IIC_0_sda_io]When built the resources taken account for about 20% of the logic resources, 36% of the memory resources, leaving plenty for future expansion.
The software application in Vitis creates a simple Command Line Interface, this is split into a number of sections
CLI – This folder contains all of the features necessary to initialise the AXI UART Lite and receive commands over the serial link. This processes commands the commands are very simple read uses the command r and write uses the command w, these are followed by the address offset (offset from the lowest AXI Address) and in the case of write then the command to write. The CLI also has a section which processes commands to be sent over the I2C network.
IIC – This folder configures the AXI IIC to provide low level access over the AXI IIC.
The CLI then runs in a loop for ever processing commands as they are received, handling any incorrect commands and preventing the system from locking up
else if (strcmp(receive_buffer, "iic_temp") == 0)
{
u8 addr = 0x32;
u8 data[4] = {0x00,0x00,0x00,0x04};
u8 rx[2];
u16 temp_reg;
float temp;
XIic_DynSend(IIC_BASE_ADDRESS, addr,
data, sizeof(data), XIIC_REPEATED_START);
XIic_DynRecv(IIC_BASE_ADDRESS, addr,
rx, 2);
temp_reg = rx[1]<<8 | rx[0];
temp = (( (float) temp_reg * 509.3140064) / 65536 ) - 280.23087870;
xil_printf_float(temp);
}
Both the hardware design and the software design are available on my GitHub here.
When we connect up the Spartan 7 Tile, to the ZCU106 we can issue commands and see the user LEDs on the Tile change as we control them. We can also send commands across the IIC to the ZCU106 System Monitor and report the results.
As we can see this working as expected in the images above, this showcases a excellent use case for smaller FPGAs such as the Spartan 7. The power taken is also very low, at 560 mW.
However that is with one user LED illuminated we can reduce this by turning off the LED, in which case the power dissipation drops to 540 mW. Vivado reports the power dissipation on chip as 190 mW, which means other elements on the board such as the FTDI, Done LED, and driving the RS232 and IIC lines.
I am working on a more complex example which also connects the tile to a SMBus power supply demo board as well to configure and control the power supplies present on that from the Spartan 7 Tile. That requires another IIC IP core as the I2C bus has conflicting addresses with the System Monitor.
Once that project is completed I will come back and provide an updated blog.
Workshops and Webinars
If you enjoyed the blog why not take a look at the free webinars, workshops and training courses we have created over the years. Highlights include
Upcoming Webinars Timing, RTL Creation, FPGA Math and Mixed Signal
Professional PYNQ Learn how to use PYNQ in your developments
Introduction to Vivado learn how to use AMD Vivado
Ultra96, MiniZed & ZU1 three day course looking at HW, SW and PetaLinux
Arty Z7-20 Class looking at HW, SW and PetaLinux
Mastering MicroBlaze learn how to create MicroBlaze solutions
HLS Hero Workshop learn how to create High Level Synthesis based solutions
Perfecting Petalinux learn how to create and work with PetaLinux OS
Boards
Get an Adiuvo development board
Adiuvo Spartan 7 / RPi 2040 Embedded System Development Board
Adiuvo Spartan 7 Tile - Low Risk way to add a FPGA to your design.
Embedded System Book
Do you want to know more about designing embedded systems from scratch? Check out our book on creating embedded systems. This book will walk you through all the stages of requirements, architecture, component selection, schematics, layout, and FPGA / software design. We designed and manufactured the board at the heart of the book! The schematics and layout are available in Altium here Learn more about the board (see previous blogs on Bring up, DDR validation, USB, Sensors) and view the schematics here.
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