One of the pivotal architectural enhancements in the Versal family of devices was the introduction of the Network on Chip. Within the Versal devices, the NoC is split into a Horizontal (HNoC) and Vertical (VNoC) Network on Chip. The HNoCs are located at the top and bottom of the device and, as a result, are close to the IO banks and the integrated peripherals. The number of VNoCs depends on the device in addition to the number of DDR memory controllers.
Another unique element of the Versal architecture is the DDR memory controller (DDRMC) which includes a system-wide resource which supports both the PS and PL. The only method of access to the DDRMC is via the Network on Chip. This offers a high bandwidth, low-latency interface which supports either DDR, LPDDR4X or LPDDR4.
When we configure the NoC, we can include one or more DDRCs. Within our design elements connected to the NoC they connect via one of two interfaces either a NoC Master Unit (NMU) or NoC Slave Unit (NSU). The NMU is the point at which the transaction is initiated across the NoC, while the NSU is the element which responds to the transaction.
The NoC Packet Switch (NPS) controls and connects the NoC implementation for a particular deployment.
Once the configuration of the NoC is captured within our Vivado design, the initialization data is provided as part of the PDI. During device programming, the exact configuration of the NoC is configured using the NoC programming interface via the platform management controller.
During the operation, the NoC clock frequency is typically 1 GHz and is set via the CIPS clocking section. The NMU and NSU provide clock conversion structures to convert between the AXI interface domain and the NoC domain.
Here, we’ll take a little more in detail at the DDRMC and NoC since they form a central plank in most of our Versal designs.
Along with the DDR protocols listed above, the DDRMC supports a range of topologies from component to SO/U/R and LR DIMM. Our TE0950, for this example, has 4GB of DDR4 SRAM.
To get started, I created a project targeting the TE0950 board and then created a block diagram.
With the block diagram created from the board tab within the IP Integrator view, I selected the external memory and added it to the board.
This will provide a board connection prompt which enables us to identify the component mode and define if we want to create a new NoC with DDRMC or use an existing one. It is possible for the controller to support up to two independent or interleaved DDR interfaces.
Once the NoC is added and we run the block automation, we will see the options to implement the CIPS. Double check the memory type in the controller type is correct and click OK
This will generate a design which we can implement. The clocking for the DDRMC is supplied on the system clock NoC input. This can be sourced from a differential global clock pin on the XPIO banks or the HSM1 clock output from the CIPS module.
If we select this option, we need to make sure the HSM1 and the system clock frequencies are set to match each other.
As we validate the design as part of the HDL wrapper generation, the NoC connectivity will be defined. For this example, we can see the six NMU connections from the PS defined by the block diagram and the paths implemented in the NoC to connect to the DDRMC.
Once the design is built and the PDI is available, we can power on the TE0950 and program it using hardware manager. Once programmed, the hardware manager will show the DDR_MC status along with a lot of information on its calibration and performance. It is critical we understand what is being reported here if we are going to be working with Versal devices and developing our own boards.
For each DDR_MC, we will information which reports its calibration enabled and if there are issues with the calibration.
The most interesting element is the margin data which can be shown for either simple or complex write patterns. The complex patterns will show the worst case because the noise will be higher when the analysis is performed.
Running the analysis will show the margin for the read and write channels. It’s important to note that the dotted line does not show the minimum margin for proper operation but the size of the smallest window for comparison.
Now that we have looked at the NoC and DDRMC more closely, we will be discussing high-speed serial transceivers and the IBERT in the weeks ahead.
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