A few weeks ago, we looked at how to create a simple Versal system targeting the Trenz TE0950 development board which used the NOC to communicate with a BRAM. In this blog we are going to extend that design slightly to examine how we can use Integrated Logic Analyzers (ILA) and virtual IO (VIO) elements.
While it’s very similar to debugging on the 7 series, UltraScale and UltraScale+ devices, there are a few differences with Versal. The biggest difference can be found with the debug hub connection. With the 7 series, UltraScale and UltraScale+ device families, the debug hub connects to the JTAG boundary scan interface and the debug cores inserted within the design. The debug hub is also inserted automatically in 7 series, UltraScale and UltraScale+ devices which occurs during optimization. When we are working with Versal, the debug hub connects between the AXI4 master interface of the CIPS and the debug cores within the design. Unlike in previous versions where the debug cores used proprietary interfaces to connect to the debug hub, the Versal debug cores leverage AXI4-Stream interfaces. Of course, what this means is that we must have a CIPS block present in our design to enable the connection to the AXI4 master. Insertion of the debug hub in the Versal design can occur either automatically or manually. If you are using a design which implements DFX, you need to include the debug hub manually.
Other differences include the AXI-Stream ILA since the IP we instantiate now combines both ILA and system ILA capabilities. Within the AXI4-Stream ILA, we are also able to select where the samples are stored – either in BRAM or URAM.
The Versal architecture does also not include a JTAG to AXI IP, however, this functionality can be easily implemented using the Debug Access Port and Debug Packet Controller.
Just as before, we can debug signals and interfaces in our design using a range of different approaches.
Insert the ILA within a IP integrator block diagram
Mark the signal(s) within the HDL as for debug (see how here)
Insert the ILA in the post synthesis netlist by marking signals for debug
Use the debug Wizard
Using XDC constraints
The debug core will be automatically inserted during the optimization stage of the implementation if Vivado does not detect a debug hub already within the design.
If the ILA or VIO is to be connected to a debug hub manually, we need to enable the AXI4-Stream interface on the advanced option tab of the AXI4-Stream ILA/VIO and connect it to the hub.
As stated above, for this example I have added in a AXI4-Stream ILA to the previous design and configured it to monitor the AXI4 output from the NOC (Slot 0 ) and the BRAM interface (Slot 1). This will show the mix of system and traditional ILA.
Since we are not using DFX, we can use automatic debug hub insertion in this instance. Once the device image is built, we can export this and update our simple SW design to include the new design.
Using the debug capabilities of Vitis to download the device image and software, we are able to open the hardware manager in Vivado and connect to the ILA just inserted.
Setting a trigger on the AXI interface for a write operation and running the application software results in a simple capture of the transactions.
In this simple transfer, we can see the AXI write transaction in addition to the BRAM write accesses.
This summarizes how we can implement ILA within the Versal architecture at a basic level. The key thing to understand is the slight differences between the previous devices and Versal and hopefully that is clearer now.
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